Cortex.Wire.PortLinearity

On this page
  1. Overview
  2. Context
  3. Theorem Split
  4. Source Linear Port Graphs
  5. Certified Source Contraction
  6. Certified Bulk Contraction
  7. Port Instances And Uses
  8. Actualized Port Graphs
  9. Compiler Port-Use Witnesses
  10. Selected-Branch Preservation
Imports
import Mathlib.Data.Finset.Basic import Cortex.Graph.Relation import Cortex.Wire.Select

Overview

Proof-facing model of Wire source and closed actualized port linearity.

Context

Paper 5 and the Wire reference make port consumption linear at the actualized port-instance boundary. The linear unit is not a contract type and not a node: it is a named port on a concrete actualized node. A closed actualized graph must account for both sides of value flow:

  • every output port has exactly one consumer, either one value-flow edge or one terminal egress, sink, or exported-boundary discharge;
  • every input port has exactly one producer, through one value-flow edge.

This module has two deliberately separate layers:

  1. LinearPortGraph is the source-level carrier above Mokhov relations. It proves preservation for already-certified source objects and single-pair contractions, not admission of raw Wire => syntax.
  2. PortUseWitness is the closed actualized proof witness that the compiler or admission layer must eventually produce. Its input and output domains are caller-supplied finite sets; this module does not claim they already match a concrete Haskell topology.

Raw => matching determinism, repeated-reference rejection, source make/* expansion into certified objects, and executable projection into the closed actualized view remain correspondence obligations tracked outside this file.

Theorem Split

The source section defines LinearPortGraph, PortLinear, forgetPorts, certified overlay, certified contraction, and certified bulk contraction. The actualized section defines PortUseWitness; portUseWitness_toGraph_closedPortLinear turns a supplied witness domain into an ActualizedPortGraph satisfying ClosedPortLinear.

namespace Cortex.Wire

Source Linear Port Graphs

SourcePortInstance identifies one named source-level port on one Wire/Circuit node.

Unlike ActualizedPortInstance, this lives before lowering to the closed actualized runtime view. It is the proof-side carrier for ADR 0047's typed-frontier endpoint resources.

structure SourcePortInstance (node port : Type) where

Source node that owns this port instance.

node : node

Source port label or proof-side identity on that node.

port : port deriving DecidableEq, Repr

LinearPortGraph is the source Wire/Circuit port graph above Mokhov relations.

The carrier keeps node identities, source input/output port instances, open frontier endpoints, and port-to-port edges. Its forgetPorts lowering erases port identity and exposes only the node-level relation topology.

structure LinearPortGraph (node outputPort inputPort : Type) [DecidableEq node] [DecidableEq outputPort] [DecidableEq inputPort] where

Nodes present in the source graph.

nodes : Finset node

Source output port instances owned by graph nodes.

outputs : Finset (SourcePortInstance node outputPort)

Source input port instances owned by graph nodes.

inputs : Finset (SourcePortInstance node inputPort)

Open output frontier endpoints not consumed by an internal edge.

exposedOutputs : Finset (SourcePortInstance node outputPort)

Open input frontier endpoints not produced by an internal edge.

exposedInputs : Finset (SourcePortInstance node inputPort)

Source port edges from output instances to input instances.

portEdges : Finset (SourcePortInstance node outputPort × SourcePortInstance node inputPort)

Every output port belongs to a graph node.

output_nodes : ∀ output, output ∈ outputs → output.node ∈ nodes

Every input port belongs to a graph node.

input_nodes : ∀ input, input ∈ inputs → input.node ∈ nodes

Exposed output endpoints are graph outputs.

exposedOutput_mem : ∀ output, output ∈ exposedOutputs → output ∈ outputs

Exposed input endpoints are graph inputs.

exposedInput_mem : ∀ input, input ∈ exposedInputs → input ∈ inputs

Every port-edge source is a graph output.

edge_output_mem : ∀ edge, edge ∈ portEdges → edge.1 ∈ outputs

Every port-edge target is a graph input.

edge_input_mem : ∀ edge, edge ∈ portEdges → edge.2 ∈ inputsnamespace LinearPortGraphvariable {node outputPort inputPort : Type}variable [DecidableEq node]variable [DecidableEq outputPort]variable [DecidableEq inputPort]

Outputs from left and right are disjoint as source endpoint resources.

def OutputDisjoint (left right : LinearPortGraph node outputPort inputPort) : Prop := ∀ output, output ∈ left.outputs → output ∈ right.outputs → False

Inputs from left and right are disjoint as source endpoint resources.

def InputDisjoint (left right : LinearPortGraph node outputPort inputPort) : Prop := ∀ input, input ∈ left.inputs → input ∈ right.inputs → False

Nodes from left and right are disjoint as source graph identities.

def NodeDisjoint (left right : LinearPortGraph node outputPort inputPort) : Prop := ∀ graphNode, graphNode ∈ left.nodes → graphNode ∈ right.nodes → False

Source graph domains are disjoint at node and endpoint-resource levels.

NodeDisjoint is the load-bearing source-reference condition; the endpoint fields are kept explicit so callers can use the exact port direction without re-deriving it from node ownership.

def DomainDisjoint (left right : LinearPortGraph node outputPort inputPort) : Prop := NodeDisjoint left right ∧ OutputDisjoint left right ∧ InputDisjoint left right

PortLinear graph states the certified source endpoint rule from ADR 0047.

Each output endpoint is either open on the output frontier or consumed by exactly one internal edge; each input endpoint is either open on the input frontier or produced by exactly one internal edge.

def PortLinear (graph : LinearPortGraph node outputPort inputPort) : Prop := (∀ output, output ∈ graph.outputs → (output ∈ graph.exposedOutputs ∧ graph.portEdges.filter (fun edge => edge.1 = output) = ∅) ∨ (output ∉ graph.exposedOutputs ∧ ∃ input, input ∈ graph.inputs ∧ graph.portEdges.filter (fun edge => edge.1 = output) = {(output, input)})) ∧ (∀ input, input ∈ graph.inputs → (input ∈ graph.exposedInputs ∧ graph.portEdges.filter (fun edge => edge.2 = input) = ∅) ∨ (input ∉ graph.exposedInputs ∧ ∃ output, output ∈ graph.outputs ∧ graph.portEdges.filter (fun edge => edge.2 = input) = {(output, input)}))

Forget source port identity and expose only node-level relation topology.

def forgetPorts (graph : LinearPortGraph node outputPort inputPort) : Cortex.Graph.Relation node := { vertices := graph.nodes edges := graph.portEdges.image (fun edge => (edge.1.node, edge.2.node)) }

Source port graphs lower to endpoint-closed node relations.

theorem forgetPorts_edgeEndpointsInVertices (graph : LinearPortGraph node outputPort inputPort) : Cortex.Graph.Relation.EdgeEndpointsInVertices graph.forgetPorts := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPort⊢ graph.forgetPorts.EdgeEndpointsInVertices intro edge node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortedge:node × nodehEdge:edge ∈ graph.forgetPorts.edges⊢ edge.1 ∈ graph.forgetPorts.vertices ∧ edge.2 ∈ graph.forgetPorts.vertices node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortedge:node × nodehEdge:edge ∈ Finset.image (fun edge => (edge.1.node, edge.2.node)) graph.portEdges⊢ edge.1 ∈ graph.nodes ∧ edge.2 ∈ graph.nodes node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortedge:node × nodehEdge:edge ∈ Finset.image (fun edge => (edge.1.node, edge.2.node)) graph.portEdgesportEdge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthPortEdge:portEdge ∈ graph.portEdgeshEq:(portEdge.1.node, portEdge.2.node) = edge⊢ edge.1 ∈ graph.nodes ∧ edge.2 ∈ graph.nodes node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortportEdge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthPortEdge:portEdge ∈ graph.portEdgeshEdge:(portEdge.1.node, portEdge.2.node) ∈ Finset.image (fun edge => (edge.1.node, edge.2.node)) graph.portEdges⊢ (portEdge.1.node, portEdge.2.node).1 ∈ graph.nodes ∧ (portEdge.1.node, portEdge.2.node).2 ∈ graph.nodes All goals completed! 🐙

Overlay of source port graphs preserves all endpoint/resource domains by union.

def overlay (left right : LinearPortGraph node outputPort inputPort) : LinearPortGraph node outputPort inputPort where nodes := left.nodes ∪ right.nodes outputs := left.outputs ∪ right.outputs inputs := left.inputs ∪ right.inputs exposedOutputs := left.exposedOutputs ∪ right.exposedOutputs exposedInputs := left.exposedInputs ∪ right.exposedInputs portEdges := left.portEdges ∪ right.portEdges output_nodes := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPort⊢ ∀ output ∈ left.outputs ∪ right.outputs, output.node ∈ left.nodes ∪ right.nodes intro output node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputs ∪ right.outputs⊢ output.node ∈ left.nodes ∪ right.nodes node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputs ∪ right.outputshLeft:output ∈ left.outputs⊢ output.node ∈ left.nodes ∪ right.nodesnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputs ∪ right.outputshRight:output ∈ right.outputs⊢ output.node ∈ left.nodes ∪ right.nodes node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputs ∪ right.outputshLeft:output ∈ left.outputs⊢ output.node ∈ left.nodes ∪ right.nodes All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputs ∪ right.outputshRight:output ∈ right.outputs⊢ output.node ∈ left.nodes ∪ right.nodes All goals completed! 🐙 input_nodes := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPort⊢ ∀ input ∈ left.inputs ∪ right.inputs, input.node ∈ left.nodes ∪ right.nodes intro input node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthInput:input ∈ left.inputs ∪ right.inputs⊢ input.node ∈ left.nodes ∪ right.nodes node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthInput:input ∈ left.inputs ∪ right.inputshLeft:input ∈ left.inputs⊢ input.node ∈ left.nodes ∪ right.nodesnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthInput:input ∈ left.inputs ∪ right.inputshRight:input ∈ right.inputs⊢ input.node ∈ left.nodes ∪ right.nodes node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthInput:input ∈ left.inputs ∪ right.inputshLeft:input ∈ left.inputs⊢ input.node ∈ left.nodes ∪ right.nodes All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthInput:input ∈ left.inputs ∪ right.inputshRight:input ∈ right.inputs⊢ input.node ∈ left.nodes ∪ right.nodes All goals completed! 🐙 exposedOutput_mem := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPort⊢ ∀ output ∈ left.exposedOutputs ∪ right.exposedOutputs, output ∈ left.outputs ∪ right.outputs intro output node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthOutput:output ∈ left.exposedOutputs ∪ right.exposedOutputs⊢ output ∈ left.outputs ∪ right.outputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthOutput:output ∈ left.exposedOutputs ∪ right.exposedOutputshLeft:output ∈ left.exposedOutputs⊢ output ∈ left.outputs ∪ right.outputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthOutput:output ∈ left.exposedOutputs ∪ right.exposedOutputshRight:output ∈ right.exposedOutputs⊢ output ∈ left.outputs ∪ right.outputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthOutput:output ∈ left.exposedOutputs ∪ right.exposedOutputshLeft:output ∈ left.exposedOutputs⊢ output ∈ left.outputs ∪ right.outputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthOutput:output ∈ left.exposedOutputs ∪ right.exposedOutputshRight:output ∈ right.exposedOutputs⊢ output ∈ left.outputs ∪ right.outputs All goals completed! 🐙 exposedInput_mem := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPort⊢ ∀ input ∈ left.exposedInputs ∪ right.exposedInputs, input ∈ left.inputs ∪ right.inputs intro input node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthInput:input ∈ left.exposedInputs ∪ right.exposedInputs⊢ input ∈ left.inputs ∪ right.inputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthInput:input ∈ left.exposedInputs ∪ right.exposedInputshLeft:input ∈ left.exposedInputs⊢ input ∈ left.inputs ∪ right.inputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthInput:input ∈ left.exposedInputs ∪ right.exposedInputshRight:input ∈ right.exposedInputs⊢ input ∈ left.inputs ∪ right.inputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthInput:input ∈ left.exposedInputs ∪ right.exposedInputshLeft:input ∈ left.exposedInputs⊢ input ∈ left.inputs ∪ right.inputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthInput:input ∈ left.exposedInputs ∪ right.exposedInputshRight:input ∈ right.exposedInputs⊢ input ∈ left.inputs ∪ right.inputs All goals completed! 🐙 edge_output_mem := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPort⊢ ∀ edge ∈ left.portEdges ∪ right.portEdges, edge.1 ∈ left.outputs ∪ right.outputs intro edge node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ left.portEdges ∪ right.portEdges⊢ edge.1 ∈ left.outputs ∪ right.outputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ left.portEdges ∪ right.portEdgeshLeft:edge ∈ left.portEdges⊢ edge.1 ∈ left.outputs ∪ right.outputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ left.portEdges ∪ right.portEdgeshRight:edge ∈ right.portEdges⊢ edge.1 ∈ left.outputs ∪ right.outputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ left.portEdges ∪ right.portEdgeshLeft:edge ∈ left.portEdges⊢ edge.1 ∈ left.outputs ∪ right.outputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ left.portEdges ∪ right.portEdgeshRight:edge ∈ right.portEdges⊢ edge.1 ∈ left.outputs ∪ right.outputs All goals completed! 🐙 edge_input_mem := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPort⊢ ∀ edge ∈ left.portEdges ∪ right.portEdges, edge.2 ∈ left.inputs ∪ right.inputs intro edge node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ left.portEdges ∪ right.portEdges⊢ edge.2 ∈ left.inputs ∪ right.inputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ left.portEdges ∪ right.portEdgeshLeft:edge ∈ left.portEdges⊢ edge.2 ∈ left.inputs ∪ right.inputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ left.portEdges ∪ right.portEdgeshRight:edge ∈ right.portEdges⊢ edge.2 ∈ left.inputs ∪ right.inputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ left.portEdges ∪ right.portEdgeshLeft:edge ∈ left.portEdges⊢ edge.2 ∈ left.inputs ∪ right.inputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ left.portEdges ∪ right.portEdgeshRight:edge ∈ right.portEdges⊢ edge.2 ∈ left.inputs ∪ right.inputs All goals completed! 🐙

Forgetting ports commutes with source overlay.

theorem forgetPorts_overlay (left right : LinearPortGraph node outputPort inputPort) : (overlay left right).forgetPorts = Cortex.Graph.Relation.overlay left.forgetPorts right.forgetPorts := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPort⊢ (left.overlay right).forgetPorts = left.forgetPorts.overlay right.forgetPorts node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortx:node⊢ x ∈ (left.overlay right).forgetPorts.vertices ↔ x ∈ (left.forgetPorts.overlay right.forgetPorts).verticesnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortx:node × node⊢ x ∈ (left.overlay right).forgetPorts.edges ↔ x ∈ (left.forgetPorts.overlay right.forgetPorts).edges node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortx:node⊢ x ∈ (left.overlay right).forgetPorts.vertices ↔ x ∈ (left.forgetPorts.overlay right.forgetPorts).verticesnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortx:node × node⊢ x ∈ (left.overlay right).forgetPorts.edges ↔ x ∈ (left.forgetPorts.overlay right.forgetPorts).edges All goals completed! 🐙

Filtering overlay edges by a left-owned output ignores the right edge set.

theorem overlay_filter_output_left (left right : LinearPortGraph node outputPort inputPort) {output : SourcePortInstance node outputPort} (hNotRight : output ∉ right.outputs) : (overlay left right).portEdges.filter (fun edge => edge.1 = output) = left.portEdges.filter (fun edge => edge.1 = output) := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotRight:output ∉ right.outputs⊢ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {edge ∈ left.portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotRight:output ∉ right.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output} ↔ edge ∈ {edge ∈ left.portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotRight:output ∉ right.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output} → edge ∈ {edge ∈ left.portEdges | edge.1 = output}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotRight:output ∉ right.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ left.portEdges | edge.1 = output} → edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotRight:output ∉ right.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output} → edge ∈ {edge ∈ left.portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotRight:output ∉ right.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output}⊢ edge ∈ {edge ∈ left.portEdges | edge.1 = output} have hMember : edge ∈ left.portEdges ∪ right.portEdges ∧ edge.1 = output := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotRight:output ∉ right.outputs⊢ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {edge ∈ left.portEdges | edge.1 = output} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotRight:output ∉ right.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshSource:edge.1 = output⊢ edge ∈ {edge ∈ left.portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotRight:output ∉ right.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshSource:edge.1 = outputhLeft:edge ∈ left.portEdges⊢ edge ∈ {edge ∈ left.portEdges | edge.1 = output}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotRight:output ∉ right.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshSource:edge.1 = outputhRight:edge ∈ right.portEdges⊢ edge ∈ {edge ∈ left.portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotRight:output ∉ right.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshSource:edge.1 = outputhLeft:edge ∈ left.portEdges⊢ edge ∈ {edge ∈ left.portEdges | edge.1 = output} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotRight:output ∉ right.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshSource:edge.1 = outputhRight:edge ∈ right.portEdges⊢ edge ∈ {edge ∈ left.portEdges | edge.1 = output} have hRightOutput : output ∈ right.outputs := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotRight:output ∉ right.outputs⊢ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {edge ∈ left.portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotRight:output ∉ right.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshSource:edge.1 = outputhRight:edge ∈ right.portEdges⊢ edge.1 ∈ right.outputs All goals completed! 🐙 All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotRight:output ∉ right.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ left.portEdges | edge.1 = output} → edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotRight:output ∉ right.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ left.portEdges | edge.1 = output}⊢ edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output} have hMember : edge ∈ left.portEdges ∧ edge.1 = output := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotRight:output ∉ right.outputs⊢ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {edge ∈ left.portEdges | edge.1 = output} All goals completed! 🐙 All goals completed! 🐙

Filtering overlay edges by a right-owned output ignores the left edge set.

theorem overlay_filter_output_right (left right : LinearPortGraph node outputPort inputPort) {output : SourcePortInstance node outputPort} (hNotLeft : output ∉ left.outputs) : (overlay left right).portEdges.filter (fun edge => edge.1 = output) = right.portEdges.filter (fun edge => edge.1 = output) := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotLeft:output ∉ left.outputs⊢ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {edge ∈ right.portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotLeft:output ∉ left.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output} ↔ edge ∈ {edge ∈ right.portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotLeft:output ∉ left.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output} → edge ∈ {edge ∈ right.portEdges | edge.1 = output}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotLeft:output ∉ left.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ right.portEdges | edge.1 = output} → edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotLeft:output ∉ left.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output} → edge ∈ {edge ∈ right.portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotLeft:output ∉ left.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output}⊢ edge ∈ {edge ∈ right.portEdges | edge.1 = output} have hMember : edge ∈ left.portEdges ∪ right.portEdges ∧ edge.1 = output := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotLeft:output ∉ left.outputs⊢ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {edge ∈ right.portEdges | edge.1 = output} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotLeft:output ∉ left.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshSource:edge.1 = output⊢ edge ∈ {edge ∈ right.portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotLeft:output ∉ left.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshSource:edge.1 = outputhLeft:edge ∈ left.portEdges⊢ edge ∈ {edge ∈ right.portEdges | edge.1 = output}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotLeft:output ∉ left.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshSource:edge.1 = outputhRight:edge ∈ right.portEdges⊢ edge ∈ {edge ∈ right.portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotLeft:output ∉ left.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshSource:edge.1 = outputhLeft:edge ∈ left.portEdges⊢ edge ∈ {edge ∈ right.portEdges | edge.1 = output} have hLeftOutput : output ∈ left.outputs := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotLeft:output ∉ left.outputs⊢ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {edge ∈ right.portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotLeft:output ∉ left.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshSource:edge.1 = outputhLeft:edge ∈ left.portEdges⊢ edge.1 ∈ left.outputs All goals completed! 🐙 All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotLeft:output ∉ left.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshSource:edge.1 = outputhRight:edge ∈ right.portEdges⊢ edge ∈ {edge ∈ right.portEdges | edge.1 = output} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotLeft:output ∉ left.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ right.portEdges | edge.1 = output} → edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotLeft:output ∉ left.outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ right.portEdges | edge.1 = output}⊢ edge ∈ {edge ∈ (left.overlay right).portEdges | edge.1 = output} have hMember : edge ∈ right.portEdges ∧ edge.1 = output := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPorthNotLeft:output ∉ left.outputs⊢ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {edge ∈ right.portEdges | edge.1 = output} All goals completed! 🐙 All goals completed! 🐙

Filtering overlay edges by a left-owned input ignores the right edge set.

theorem overlay_filter_input_left (left right : LinearPortGraph node outputPort inputPort) {input : SourcePortInstance node inputPort} (hNotRight : input ∉ right.inputs) : (overlay left right).portEdges.filter (fun edge => edge.2 = input) = left.portEdges.filter (fun edge => edge.2 = input) := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotRight:input ∉ right.inputs⊢ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {edge ∈ left.portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotRight:input ∉ right.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input} ↔ edge ∈ {edge ∈ left.portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotRight:input ∉ right.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input} → edge ∈ {edge ∈ left.portEdges | edge.2 = input}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotRight:input ∉ right.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ left.portEdges | edge.2 = input} → edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotRight:input ∉ right.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input} → edge ∈ {edge ∈ left.portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotRight:input ∉ right.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input}⊢ edge ∈ {edge ∈ left.portEdges | edge.2 = input} have hMember : edge ∈ left.portEdges ∪ right.portEdges ∧ edge.2 = input := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotRight:input ∉ right.inputs⊢ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {edge ∈ left.portEdges | edge.2 = input} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotRight:input ∉ right.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshTarget:edge.2 = input⊢ edge ∈ {edge ∈ left.portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotRight:input ∉ right.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshTarget:edge.2 = inputhLeft:edge ∈ left.portEdges⊢ edge ∈ {edge ∈ left.portEdges | edge.2 = input}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotRight:input ∉ right.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshTarget:edge.2 = inputhRight:edge ∈ right.portEdges⊢ edge ∈ {edge ∈ left.portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotRight:input ∉ right.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshTarget:edge.2 = inputhLeft:edge ∈ left.portEdges⊢ edge ∈ {edge ∈ left.portEdges | edge.2 = input} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotRight:input ∉ right.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshTarget:edge.2 = inputhRight:edge ∈ right.portEdges⊢ edge ∈ {edge ∈ left.portEdges | edge.2 = input} have hRightInput : input ∈ right.inputs := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotRight:input ∉ right.inputs⊢ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {edge ∈ left.portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotRight:input ∉ right.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshTarget:edge.2 = inputhRight:edge ∈ right.portEdges⊢ edge.2 ∈ right.inputs All goals completed! 🐙 All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotRight:input ∉ right.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ left.portEdges | edge.2 = input} → edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotRight:input ∉ right.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ left.portEdges | edge.2 = input}⊢ edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input} have hMember : edge ∈ left.portEdges ∧ edge.2 = input := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotRight:input ∉ right.inputs⊢ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {edge ∈ left.portEdges | edge.2 = input} All goals completed! 🐙 All goals completed! 🐙

Filtering overlay edges by a right-owned input ignores the left edge set.

theorem overlay_filter_input_right (left right : LinearPortGraph node outputPort inputPort) {input : SourcePortInstance node inputPort} (hNotLeft : input ∉ left.inputs) : (overlay left right).portEdges.filter (fun edge => edge.2 = input) = right.portEdges.filter (fun edge => edge.2 = input) := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotLeft:input ∉ left.inputs⊢ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {edge ∈ right.portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotLeft:input ∉ left.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input} ↔ edge ∈ {edge ∈ right.portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotLeft:input ∉ left.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input} → edge ∈ {edge ∈ right.portEdges | edge.2 = input}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotLeft:input ∉ left.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ right.portEdges | edge.2 = input} → edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotLeft:input ∉ left.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input} → edge ∈ {edge ∈ right.portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotLeft:input ∉ left.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input}⊢ edge ∈ {edge ∈ right.portEdges | edge.2 = input} have hMember : edge ∈ left.portEdges ∪ right.portEdges ∧ edge.2 = input := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotLeft:input ∉ left.inputs⊢ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {edge ∈ right.portEdges | edge.2 = input} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotLeft:input ∉ left.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshTarget:edge.2 = input⊢ edge ∈ {edge ∈ right.portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotLeft:input ∉ left.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshTarget:edge.2 = inputhLeft:edge ∈ left.portEdges⊢ edge ∈ {edge ∈ right.portEdges | edge.2 = input}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotLeft:input ∉ left.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshTarget:edge.2 = inputhRight:edge ∈ right.portEdges⊢ edge ∈ {edge ∈ right.portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotLeft:input ∉ left.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshTarget:edge.2 = inputhLeft:edge ∈ left.portEdges⊢ edge ∈ {edge ∈ right.portEdges | edge.2 = input} have hLeftInput : input ∈ left.inputs := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotLeft:input ∉ left.inputs⊢ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {edge ∈ right.portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotLeft:input ∉ left.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshTarget:edge.2 = inputhLeft:edge ∈ left.portEdges⊢ edge.2 ∈ left.inputs All goals completed! 🐙 All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotLeft:input ∉ left.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input}hUnion:edge ∈ left.portEdges ∪ right.portEdgeshTarget:edge.2 = inputhRight:edge ∈ right.portEdges⊢ edge ∈ {edge ∈ right.portEdges | edge.2 = input} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotLeft:input ∉ left.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ right.portEdges | edge.2 = input} → edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotLeft:input ∉ left.inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ right.portEdges | edge.2 = input}⊢ edge ∈ {edge ∈ (left.overlay right).portEdges | edge.2 = input} have hMember : edge ∈ right.portEdges ∧ edge.2 = input := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPortinput:SourcePortInstance node inputPorthNotLeft:input ∉ left.inputs⊢ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {edge ∈ right.portEdges | edge.2 = input} All goals completed! 🐙 All goals completed! 🐙

Source overlay preserves source port linearity when endpoint domains are disjoint.

theorem overlay_preserves_portLinear (left right : LinearPortGraph node outputPort inputPort) (hLeft : left.PortLinear) (hRight : right.PortLinear) (hDisjoint : DomainDisjoint left right) : (overlay left right).PortLinear := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint right⊢ (left.overlay right).PortLinear node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint right⊢ ∀ output ∈ (left.overlay right).outputs, output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint right⊢ ∀ input ∈ (left.overlay right).inputs, input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint right⊢ ∀ output ∈ (left.overlay right).outputs, output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} intro output node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputs⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint right⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputs⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputs⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputs⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} have hNotRight : output ∉ right.outputs := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint right⊢ (left.overlay right).PortLinear node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshRightOutput:output ∈ right.outputs⊢ False All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshLeftLinear:output ∈ left.exposedOutputs ∧ {edge ∈ left.portEdges | edge.1 = output} = ∅ ∨ output ∉ left.exposedOutputs ∧ ∃ input ∈ left.inputs, {edge ∈ left.portEdges | edge.1 = output} = {(output, input)}⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshOpen:output ∈ left.exposedOutputs ∧ {edge ∈ left.portEdges | edge.1 = output} = ∅⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshConsumed:output ∉ left.exposedOutputs ∧ ∃ input ∈ left.inputs, {edge ∈ left.portEdges | edge.1 = output} = {(output, input)}⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshOpen:output ∈ left.exposedOutputs ∧ {edge ∈ left.portEdges | edge.1 = output} = ∅⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshOpen:output ∈ left.exposedOutputs ∧ {edge ∈ left.portEdges | edge.1 = output} = ∅⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshOpen:output ∈ left.exposedOutputs ∧ {edge ∈ left.portEdges | edge.1 = output} = ∅⊢ output ∈ (left.overlay right).exposedOutputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshOpen:output ∈ left.exposedOutputs ∧ {edge ∈ left.portEdges | edge.1 = output} = ∅⊢ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshOpen:output ∈ left.exposedOutputs ∧ {edge ∈ left.portEdges | edge.1 = output} = ∅⊢ output ∈ (left.overlay right).exposedOutputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshOpen:output ∈ left.exposedOutputs ∧ {edge ∈ left.portEdges | edge.1 = output} = ∅⊢ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshOpen:output ∈ left.exposedOutputs ∧ {edge ∈ left.portEdges | edge.1 = output} = ∅⊢ {edge ∈ left.portEdges | edge.1 = output} = ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshConsumed:output ∉ left.exposedOutputs ∧ ∃ input ∈ left.inputs, {edge ∈ left.portEdges | edge.1 = output} = {(output, input)}⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshConsumed:output ∉ left.exposedOutputs ∧ ∃ input ∈ left.inputs, {edge ∈ left.portEdges | edge.1 = output} = {(output, input)}⊢ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshNotExposed:output ∉ left.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ left.inputshEdges:{edge ∈ left.portEdges | edge.1 = output} = {(output, input)}⊢ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshNotExposed:output ∉ left.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ left.inputshEdges:{edge ∈ left.portEdges | edge.1 = output} = {(output, input)}⊢ output ∉ (left.overlay right).exposedOutputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshNotExposed:output ∉ left.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ left.inputshEdges:{edge ∈ left.portEdges | edge.1 = output} = {(output, input)}⊢ input ∈ (left.overlay right).inputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshNotExposed:output ∉ left.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ left.inputshEdges:{edge ∈ left.portEdges | edge.1 = output} = {(output, input)}⊢ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshNotExposed:output ∉ left.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ left.inputshEdges:{edge ∈ left.portEdges | edge.1 = output} = {(output, input)}⊢ output ∉ (left.overlay right).exposedOutputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshNotExposed:output ∉ left.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ left.inputshEdges:{edge ∈ left.portEdges | edge.1 = output} = {(output, input)}hExposed:output ∈ (left.overlay right).exposedOutputs⊢ False node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshNotExposed:output ∉ left.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ left.inputshEdges:{edge ∈ left.portEdges | edge.1 = output} = {(output, input)}hExposed:output ∈ (left.overlay right).exposedOutputshLeftExposed:output ∈ left.exposedOutputs⊢ Falsenode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshNotExposed:output ∉ left.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ left.inputshEdges:{edge ∈ left.portEdges | edge.1 = output} = {(output, input)}hExposed:output ∈ (left.overlay right).exposedOutputshRightExposed:output ∈ right.exposedOutputs⊢ False node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshNotExposed:output ∉ left.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ left.inputshEdges:{edge ∈ left.portEdges | edge.1 = output} = {(output, input)}hExposed:output ∈ (left.overlay right).exposedOutputshLeftExposed:output ∈ left.exposedOutputs⊢ False All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshNotExposed:output ∉ left.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ left.inputshEdges:{edge ∈ left.portEdges | edge.1 = output} = {(output, input)}hExposed:output ∈ (left.overlay right).exposedOutputshRightExposed:output ∈ right.exposedOutputs⊢ False All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshNotExposed:output ∉ left.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ left.inputshEdges:{edge ∈ left.portEdges | edge.1 = output} = {(output, input)}⊢ input ∈ (left.overlay right).inputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshNotExposed:output ∉ left.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ left.inputshEdges:{edge ∈ left.portEdges | edge.1 = output} = {(output, input)}⊢ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthLeftOutput:output ∈ left.outputshNotRight:output ∉ right.outputshNotExposed:output ∉ left.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ left.inputshEdges:{edge ∈ left.portEdges | edge.1 = output} = {(output, input)}⊢ {edge ∈ left.portEdges | edge.1 = output} = {(output, input)} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputs⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} have hNotLeft : output ∉ left.outputs := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint right⊢ (left.overlay right).PortLinear node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshLeftOutput:output ∈ left.outputs⊢ False All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshRightLinear:output ∈ right.exposedOutputs ∧ {edge ∈ right.portEdges | edge.1 = output} = ∅ ∨ output ∉ right.exposedOutputs ∧ ∃ input ∈ right.inputs, {edge ∈ right.portEdges | edge.1 = output} = {(output, input)}⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshOpen:output ∈ right.exposedOutputs ∧ {edge ∈ right.portEdges | edge.1 = output} = ∅⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshConsumed:output ∉ right.exposedOutputs ∧ ∃ input ∈ right.inputs, {edge ∈ right.portEdges | edge.1 = output} = {(output, input)}⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshOpen:output ∈ right.exposedOutputs ∧ {edge ∈ right.portEdges | edge.1 = output} = ∅⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshOpen:output ∈ right.exposedOutputs ∧ {edge ∈ right.portEdges | edge.1 = output} = ∅⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshOpen:output ∈ right.exposedOutputs ∧ {edge ∈ right.portEdges | edge.1 = output} = ∅⊢ output ∈ (left.overlay right).exposedOutputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshOpen:output ∈ right.exposedOutputs ∧ {edge ∈ right.portEdges | edge.1 = output} = ∅⊢ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshOpen:output ∈ right.exposedOutputs ∧ {edge ∈ right.portEdges | edge.1 = output} = ∅⊢ output ∈ (left.overlay right).exposedOutputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshOpen:output ∈ right.exposedOutputs ∧ {edge ∈ right.portEdges | edge.1 = output} = ∅⊢ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshOpen:output ∈ right.exposedOutputs ∧ {edge ∈ right.portEdges | edge.1 = output} = ∅⊢ {edge ∈ right.portEdges | edge.1 = output} = ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshConsumed:output ∉ right.exposedOutputs ∧ ∃ input ∈ right.inputs, {edge ∈ right.portEdges | edge.1 = output} = {(output, input)}⊢ output ∈ (left.overlay right).exposedOutputs ∧ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = ∅ ∨ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshConsumed:output ∉ right.exposedOutputs ∧ ∃ input ∈ right.inputs, {edge ∈ right.portEdges | edge.1 = output} = {(output, input)}⊢ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshNotExposed:output ∉ right.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ right.inputshEdges:{edge ∈ right.portEdges | edge.1 = output} = {(output, input)}⊢ output ∉ (left.overlay right).exposedOutputs ∧ ∃ input ∈ (left.overlay right).inputs, {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshNotExposed:output ∉ right.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ right.inputshEdges:{edge ∈ right.portEdges | edge.1 = output} = {(output, input)}⊢ output ∉ (left.overlay right).exposedOutputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshNotExposed:output ∉ right.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ right.inputshEdges:{edge ∈ right.portEdges | edge.1 = output} = {(output, input)}⊢ input ∈ (left.overlay right).inputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshNotExposed:output ∉ right.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ right.inputshEdges:{edge ∈ right.portEdges | edge.1 = output} = {(output, input)}⊢ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshNotExposed:output ∉ right.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ right.inputshEdges:{edge ∈ right.portEdges | edge.1 = output} = {(output, input)}⊢ output ∉ (left.overlay right).exposedOutputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshNotExposed:output ∉ right.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ right.inputshEdges:{edge ∈ right.portEdges | edge.1 = output} = {(output, input)}hExposed:output ∈ (left.overlay right).exposedOutputs⊢ False node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshNotExposed:output ∉ right.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ right.inputshEdges:{edge ∈ right.portEdges | edge.1 = output} = {(output, input)}hExposed:output ∈ (left.overlay right).exposedOutputshLeftExposed:output ∈ left.exposedOutputs⊢ Falsenode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshNotExposed:output ∉ right.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ right.inputshEdges:{edge ∈ right.portEdges | edge.1 = output} = {(output, input)}hExposed:output ∈ (left.overlay right).exposedOutputshRightExposed:output ∈ right.exposedOutputs⊢ False node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshNotExposed:output ∉ right.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ right.inputshEdges:{edge ∈ right.portEdges | edge.1 = output} = {(output, input)}hExposed:output ∈ (left.overlay right).exposedOutputshLeftExposed:output ∈ left.exposedOutputs⊢ False All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshNotExposed:output ∉ right.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ right.inputshEdges:{edge ∈ right.portEdges | edge.1 = output} = {(output, input)}hExposed:output ∈ (left.overlay right).exposedOutputshRightExposed:output ∈ right.exposedOutputs⊢ False All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshNotExposed:output ∉ right.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ right.inputshEdges:{edge ∈ right.portEdges | edge.1 = output} = {(output, input)}⊢ input ∈ (left.overlay right).inputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshNotExposed:output ∉ right.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ right.inputshEdges:{edge ∈ right.portEdges | edge.1 = output} = {(output, input)}⊢ {edge ∈ (left.overlay right).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightoutput:SourcePortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshNotExposed:output ∉ right.exposedOutputsinput:SourcePortInstance node inputPorthInput:input ∈ right.inputshEdges:{edge ∈ right.portEdges | edge.1 = output} = {(output, input)}⊢ {edge ∈ right.portEdges | edge.1 = output} = {(output, input)} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint right⊢ ∀ input ∈ (left.overlay right).inputs, input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} intro input node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputs⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint right⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputs⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputs⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputs⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} have hNotRight : input ∉ right.inputs := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint right⊢ (left.overlay right).PortLinear node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshRightInput:input ∈ right.inputs⊢ False All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshLeftLinear:input ∈ left.exposedInputs ∧ {edge ∈ left.portEdges | edge.2 = input} = ∅ ∨ input ∉ left.exposedInputs ∧ ∃ output ∈ left.outputs, {edge ∈ left.portEdges | edge.2 = input} = {(output, input)}⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshOpen:input ∈ left.exposedInputs ∧ {edge ∈ left.portEdges | edge.2 = input} = ∅⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshProduced:input ∉ left.exposedInputs ∧ ∃ output ∈ left.outputs, {edge ∈ left.portEdges | edge.2 = input} = {(output, input)}⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshOpen:input ∈ left.exposedInputs ∧ {edge ∈ left.portEdges | edge.2 = input} = ∅⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshOpen:input ∈ left.exposedInputs ∧ {edge ∈ left.portEdges | edge.2 = input} = ∅⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshOpen:input ∈ left.exposedInputs ∧ {edge ∈ left.portEdges | edge.2 = input} = ∅⊢ input ∈ (left.overlay right).exposedInputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshOpen:input ∈ left.exposedInputs ∧ {edge ∈ left.portEdges | edge.2 = input} = ∅⊢ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshOpen:input ∈ left.exposedInputs ∧ {edge ∈ left.portEdges | edge.2 = input} = ∅⊢ input ∈ (left.overlay right).exposedInputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshOpen:input ∈ left.exposedInputs ∧ {edge ∈ left.portEdges | edge.2 = input} = ∅⊢ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshOpen:input ∈ left.exposedInputs ∧ {edge ∈ left.portEdges | edge.2 = input} = ∅⊢ {edge ∈ left.portEdges | edge.2 = input} = ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshProduced:input ∉ left.exposedInputs ∧ ∃ output ∈ left.outputs, {edge ∈ left.portEdges | edge.2 = input} = {(output, input)}⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshProduced:input ∉ left.exposedInputs ∧ ∃ output ∈ left.outputs, {edge ∈ left.portEdges | edge.2 = input} = {(output, input)}⊢ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshNotExposed:input ∉ left.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputshEdges:{edge ∈ left.portEdges | edge.2 = input} = {(output, input)}⊢ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshNotExposed:input ∉ left.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputshEdges:{edge ∈ left.portEdges | edge.2 = input} = {(output, input)}⊢ input ∉ (left.overlay right).exposedInputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshNotExposed:input ∉ left.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputshEdges:{edge ∈ left.portEdges | edge.2 = input} = {(output, input)}⊢ output ∈ (left.overlay right).outputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshNotExposed:input ∉ left.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputshEdges:{edge ∈ left.portEdges | edge.2 = input} = {(output, input)}⊢ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshNotExposed:input ∉ left.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputshEdges:{edge ∈ left.portEdges | edge.2 = input} = {(output, input)}⊢ input ∉ (left.overlay right).exposedInputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshNotExposed:input ∉ left.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputshEdges:{edge ∈ left.portEdges | edge.2 = input} = {(output, input)}hExposed:input ∈ (left.overlay right).exposedInputs⊢ False node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshNotExposed:input ∉ left.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputshEdges:{edge ∈ left.portEdges | edge.2 = input} = {(output, input)}hExposed:input ∈ (left.overlay right).exposedInputshLeftExposed:input ∈ left.exposedInputs⊢ Falsenode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshNotExposed:input ∉ left.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputshEdges:{edge ∈ left.portEdges | edge.2 = input} = {(output, input)}hExposed:input ∈ (left.overlay right).exposedInputshRightExposed:input ∈ right.exposedInputs⊢ False node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshNotExposed:input ∉ left.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputshEdges:{edge ∈ left.portEdges | edge.2 = input} = {(output, input)}hExposed:input ∈ (left.overlay right).exposedInputshLeftExposed:input ∈ left.exposedInputs⊢ False All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshNotExposed:input ∉ left.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputshEdges:{edge ∈ left.portEdges | edge.2 = input} = {(output, input)}hExposed:input ∈ (left.overlay right).exposedInputshRightExposed:input ∈ right.exposedInputs⊢ False All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshNotExposed:input ∉ left.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputshEdges:{edge ∈ left.portEdges | edge.2 = input} = {(output, input)}⊢ output ∈ (left.overlay right).outputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshNotExposed:input ∉ left.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputshEdges:{edge ∈ left.portEdges | edge.2 = input} = {(output, input)}⊢ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthLeftInput:input ∈ left.inputshNotRight:input ∉ right.inputshNotExposed:input ∉ left.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ left.outputshEdges:{edge ∈ left.portEdges | edge.2 = input} = {(output, input)}⊢ {edge ∈ left.portEdges | edge.2 = input} = {(output, input)} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputs⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} have hNotLeft : input ∉ left.inputs := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint right⊢ (left.overlay right).PortLinear node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshLeftInput:input ∈ left.inputs⊢ False All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshRightLinear:input ∈ right.exposedInputs ∧ {edge ∈ right.portEdges | edge.2 = input} = ∅ ∨ input ∉ right.exposedInputs ∧ ∃ output ∈ right.outputs, {edge ∈ right.portEdges | edge.2 = input} = {(output, input)}⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshOpen:input ∈ right.exposedInputs ∧ {edge ∈ right.portEdges | edge.2 = input} = ∅⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshProduced:input ∉ right.exposedInputs ∧ ∃ output ∈ right.outputs, {edge ∈ right.portEdges | edge.2 = input} = {(output, input)}⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshOpen:input ∈ right.exposedInputs ∧ {edge ∈ right.portEdges | edge.2 = input} = ∅⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshOpen:input ∈ right.exposedInputs ∧ {edge ∈ right.portEdges | edge.2 = input} = ∅⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshOpen:input ∈ right.exposedInputs ∧ {edge ∈ right.portEdges | edge.2 = input} = ∅⊢ input ∈ (left.overlay right).exposedInputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshOpen:input ∈ right.exposedInputs ∧ {edge ∈ right.portEdges | edge.2 = input} = ∅⊢ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshOpen:input ∈ right.exposedInputs ∧ {edge ∈ right.portEdges | edge.2 = input} = ∅⊢ input ∈ (left.overlay right).exposedInputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshOpen:input ∈ right.exposedInputs ∧ {edge ∈ right.portEdges | edge.2 = input} = ∅⊢ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshOpen:input ∈ right.exposedInputs ∧ {edge ∈ right.portEdges | edge.2 = input} = ∅⊢ {edge ∈ right.portEdges | edge.2 = input} = ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshProduced:input ∉ right.exposedInputs ∧ ∃ output ∈ right.outputs, {edge ∈ right.portEdges | edge.2 = input} = {(output, input)}⊢ input ∈ (left.overlay right).exposedInputs ∧ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = ∅ ∨ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshProduced:input ∉ right.exposedInputs ∧ ∃ output ∈ right.outputs, {edge ∈ right.portEdges | edge.2 = input} = {(output, input)}⊢ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshNotExposed:input ∉ right.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ right.outputshEdges:{edge ∈ right.portEdges | edge.2 = input} = {(output, input)}⊢ input ∉ (left.overlay right).exposedInputs ∧ ∃ output ∈ (left.overlay right).outputs, {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshNotExposed:input ∉ right.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ right.outputshEdges:{edge ∈ right.portEdges | edge.2 = input} = {(output, input)}⊢ input ∉ (left.overlay right).exposedInputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshNotExposed:input ∉ right.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ right.outputshEdges:{edge ∈ right.portEdges | edge.2 = input} = {(output, input)}⊢ output ∈ (left.overlay right).outputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshNotExposed:input ∉ right.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ right.outputshEdges:{edge ∈ right.portEdges | edge.2 = input} = {(output, input)}⊢ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshNotExposed:input ∉ right.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ right.outputshEdges:{edge ∈ right.portEdges | edge.2 = input} = {(output, input)}⊢ input ∉ (left.overlay right).exposedInputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshNotExposed:input ∉ right.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ right.outputshEdges:{edge ∈ right.portEdges | edge.2 = input} = {(output, input)}hExposed:input ∈ (left.overlay right).exposedInputs⊢ False node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshNotExposed:input ∉ right.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ right.outputshEdges:{edge ∈ right.portEdges | edge.2 = input} = {(output, input)}hExposed:input ∈ (left.overlay right).exposedInputshLeftExposed:input ∈ left.exposedInputs⊢ Falsenode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshNotExposed:input ∉ right.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ right.outputshEdges:{edge ∈ right.portEdges | edge.2 = input} = {(output, input)}hExposed:input ∈ (left.overlay right).exposedInputshRightExposed:input ∈ right.exposedInputs⊢ False node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshNotExposed:input ∉ right.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ right.outputshEdges:{edge ∈ right.portEdges | edge.2 = input} = {(output, input)}hExposed:input ∈ (left.overlay right).exposedInputshLeftExposed:input ∈ left.exposedInputs⊢ False All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshNotExposed:input ∉ right.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ right.outputshEdges:{edge ∈ right.portEdges | edge.2 = input} = {(output, input)}hExposed:input ∈ (left.overlay right).exposedInputshRightExposed:input ∈ right.exposedInputs⊢ False All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshNotExposed:input ∉ right.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ right.outputshEdges:{edge ∈ right.portEdges | edge.2 = input} = {(output, input)}⊢ output ∈ (left.overlay right).outputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshNotExposed:input ∉ right.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ right.outputshEdges:{edge ∈ right.portEdges | edge.2 = input} = {(output, input)}⊢ {edge ∈ (left.overlay right).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortleft:LinearPortGraph node outputPort inputPortright:LinearPortGraph node outputPort inputPorthLeft:left.PortLinearhRight:right.PortLinearhDisjoint:left.DomainDisjoint rightinput:SourcePortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthRightInput:input ∈ right.inputshNotLeft:input ∉ left.inputshNotExposed:input ∉ right.exposedInputsoutput:SourcePortInstance node outputPorthOutput:output ∈ right.outputshEdges:{edge ∈ right.portEdges | edge.2 = input} = {(output, input)}⊢ {edge ∈ right.portEdges | edge.2 = input} = {(output, input)} All goals completed! 🐙

Certified Source Contraction

contract graph output input consumes one exposed output and one exposed input, adding the single source port edge between them.

This is the proof-side shape after elaboration has already selected one compatible pair. It is not ADR 0047's raw => matching algorithm: compatibility, counterpart cardinality, bulk contraction, and static-error cases are separate admission obligations.

def contract (graph : LinearPortGraph node outputPort inputPort) (output : SourcePortInstance node outputPort) (input : SourcePortInstance node inputPort) (hOutputExposed : output ∈ graph.exposedOutputs) (hInputExposed : input ∈ graph.exposedInputs) : LinearPortGraph node outputPort inputPort where nodes := graph.nodes outputs := graph.outputs inputs := graph.inputs exposedOutputs := graph.exposedOutputs.erase output exposedInputs := graph.exposedInputs.erase input portEdges := insert (output, input) graph.portEdges output_nodes := graph.output_nodes input_nodes := graph.input_nodes exposedOutput_mem := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ ∀ output_1 ∈ graph.exposedOutputs.erase output, output_1 ∈ graph.outputs intro candidate node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputscandidate:SourcePortInstance node outputPorthCandidate:candidate ∈ graph.exposedOutputs.erase output⊢ candidate ∈ graph.outputs All goals completed! 🐙 exposedInput_mem := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ ∀ input_1 ∈ graph.exposedInputs.erase input, input_1 ∈ graph.inputs intro candidate node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputscandidate:SourcePortInstance node inputPorthCandidate:candidate ∈ graph.exposedInputs.erase input⊢ candidate ∈ graph.inputs All goals completed! 🐙 edge_output_mem := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ ∀ edge ∈ insert (output, input) graph.portEdges, edge.1 ∈ graph.outputs intro edge node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ insert (output, input) graph.portEdges⊢ edge.1 ∈ graph.outputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ insert (output, input) graph.portEdgeshNew:edge = (output, input)⊢ edge.1 ∈ graph.outputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ insert (output, input) graph.portEdgeshOld:edge ∈ graph.portEdges⊢ edge.1 ∈ graph.outputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ insert (output, input) graph.portEdgeshNew:edge = (output, input)⊢ edge.1 ∈ graph.outputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshEdge:(output, input) ∈ insert (output, input) graph.portEdges⊢ (output, input).1 ∈ graph.outputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ insert (output, input) graph.portEdgeshOld:edge ∈ graph.portEdges⊢ edge.1 ∈ graph.outputs All goals completed! 🐙 edge_input_mem := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ ∀ edge ∈ insert (output, input) graph.portEdges, edge.2 ∈ graph.inputs intro edge node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ insert (output, input) graph.portEdges⊢ edge.2 ∈ graph.inputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ insert (output, input) graph.portEdgeshNew:edge = (output, input)⊢ edge.2 ∈ graph.inputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ insert (output, input) graph.portEdgeshOld:edge ∈ graph.portEdges⊢ edge.2 ∈ graph.inputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ insert (output, input) graph.portEdgeshNew:edge = (output, input)⊢ edge.2 ∈ graph.inputs node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshEdge:(output, input) ∈ insert (output, input) graph.portEdges⊢ (output, input).2 ∈ graph.inputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ insert (output, input) graph.portEdgeshOld:edge ∈ graph.portEdges⊢ edge.2 ∈ graph.inputs All goals completed! 🐙

Forgetting ports after certified contraction inserts the contracted node edge.

The insert is set-theoretic: if another source port edge already lowered to the same node edge, the lowered relation is unchanged.

theorem forgetPorts_contract (graph : LinearPortGraph node outputPort inputPort) (output : SourcePortInstance node outputPort) (input : SourcePortInstance node inputPort) (hOutputExposed : output ∈ graph.exposedOutputs) (hInputExposed : input ∈ graph.exposedInputs) : (graph.contract output input hOutputExposed hInputExposed).forgetPorts = { vertices := graph.forgetPorts.vertices edges := insert (output.node, input.node) graph.forgetPorts.edges } := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ (graph.contract output input hOutputExposed hInputExposed).forgetPorts = { vertices := graph.forgetPorts.vertices, edges := insert (output.node, input.node) graph.forgetPorts.edges } node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsedge:node⊢ edge ∈ (graph.contract output input hOutputExposed hInputExposed).forgetPorts.vertices ↔ edge ∈ { vertices := graph.forgetPorts.vertices, edges := insert (output.node, input.node) graph.forgetPorts.edges }.verticesnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsedge:node × node⊢ edge ∈ (graph.contract output input hOutputExposed hInputExposed).forgetPorts.edges ↔ edge ∈ { vertices := graph.forgetPorts.vertices, edges := insert (output.node, input.node) graph.forgetPorts.edges }.edges node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsedge:node⊢ edge ∈ (graph.contract output input hOutputExposed hInputExposed).forgetPorts.vertices ↔ edge ∈ { vertices := graph.forgetPorts.vertices, edges := insert (output.node, input.node) graph.forgetPorts.edges }.verticesnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsedge:node × node⊢ edge ∈ (graph.contract output input hOutputExposed hInputExposed).forgetPorts.edges ↔ edge ∈ { vertices := graph.forgetPorts.vertices, edges := insert (output.node, input.node) graph.forgetPorts.edges }.edges All goals completed! 🐙

Certified single-edge contraction preserves source port linearity.

The assumptions say the matched endpoints are exposed. Their existing edge filters are therefore empty by PortLinear; inserting exactly their edge makes them consumed exactly once, while every other endpoint keeps its previous filter.

theorem contract_preserves_portLinear (graph : LinearPortGraph node outputPort inputPort) (hLinear : graph.PortLinear) (output : SourcePortInstance node outputPort) (input : SourcePortInstance node inputPort) (hOutputExposed : output ∈ graph.exposedOutputs) (hInputExposed : input ∈ graph.exposedInputs) : (graph.contract output input hOutputExposed hInputExposed).PortLinear := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ (graph.contract output input hOutputExposed hInputExposed).PortLinear node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputs⊢ (graph.contract output input hOutputExposed hInputExposed).PortLinear node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputs⊢ (graph.contract output input hOutputExposed hInputExposed).PortLinear node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}⊢ (graph.contract output input hOutputExposed hInputExposed).PortLinear node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}⊢ (graph.contract output input hOutputExposed hInputExposed).PortLinear have hOutputNoEdges : graph.portEdges.filter (fun edge => edge.1 = output) = ∅ := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ (graph.contract output input hOutputExposed hInputExposed).PortLinear node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅⊢ {edge ∈ graph.portEdges | edge.1 = output} = ∅node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hConsumed:output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}⊢ {edge ∈ graph.portEdges | edge.1 = output} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅⊢ {edge ∈ graph.portEdges | edge.1 = output} = ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hConsumed:output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}⊢ {edge ∈ graph.portEdges | edge.1 = output} = ∅ All goals completed! 🐙 have hInputNoEdges : graph.portEdges.filter (fun edge => edge.2 = input) = ∅ := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ (graph.contract output input hOutputExposed hInputExposed).PortLinear node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅⊢ {edge ∈ graph.portEdges | edge.2 = input} = ∅node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hProduced:input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}⊢ {edge ∈ graph.portEdges | edge.2 = input} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅⊢ {edge ∈ graph.portEdges | edge.2 = input} = ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hProduced:input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}⊢ {edge ∈ graph.portEdges | edge.2 = input} = ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅⊢ ∀ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output_1} = ∅ ∨ output_1 ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ ∃ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output_1} = {(output_1, input_1)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅⊢ ∀ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input_1} = ∅ ∨ input_1 ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ ∃ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input_1} = {(output_1, input_1)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅⊢ ∀ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output_1} = ∅ ∨ output_1 ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ ∃ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output_1} = {(output_1, input_1)} intro candidate node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputs⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ ∃ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = {(candidate, input_1)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:candidate = output⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ ∃ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = {(candidate, input_1)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = output⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ ∃ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = {(candidate, input_1)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:candidate = output⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ ∃ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = {(candidate, input_1)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputs⊢ output ∈ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output} = ∅ ∨ output ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ ∃ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output} = {(output, input_1)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputs⊢ output ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ ∃ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output} = {(output, input_1)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputs⊢ output ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputs⊢ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputs⊢ output ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputs⊢ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output} ↔ edge ∈ {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output} → edge ∈ {(output, input)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {(output, input)} → edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output} → edge ∈ {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output}⊢ edge ∈ {(output, input)} have hMember : edge ∈ insert (output, input) graph.portEdges ∧ edge.1 = output := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ (graph.contract output input hOutputExposed hInputExposed).PortLinear All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = output⊢ edge ∈ {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = outputhNew:edge = (output, input)⊢ edge ∈ {(output, input)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = outputhOld:edge ∈ graph.portEdges⊢ edge ∈ {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = outputhNew:edge = (output, input)⊢ edge ∈ {(output, input)} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = outputhOld:edge ∈ graph.portEdges⊢ edge ∈ {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = outputhOld:edge ∈ graph.portEdgeshOldFiltered:edge ∈ {edge ∈ graph.portEdges | edge.1 = output}⊢ edge ∈ {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = outputhOld:edge ∈ graph.portEdgeshOldFiltered:edge ∈ ∅⊢ edge ∈ {(output, input)} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {(output, input)} → edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {(output, input)}⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output} have hEq : edge = (output, input) := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ (graph.contract output input hOutputExposed hInputExposed).PortLinear All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:output ∈ (graph.contract output input hOutputExposed hInputExposed).outputshEdge:(output, input) ∈ {(output, input)}⊢ (output, input) ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = output} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = output⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ ∃ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = {(candidate, input_1)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOldLinear:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅ ∨ candidate ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, input)}⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ ∃ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = {(candidate, input_1)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ ∃ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = {(candidate, input_1)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhConsumed:candidate ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, input)}⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ ∃ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = {(candidate, input_1)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ ∃ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = {(candidate, input_1)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedOutputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅⊢ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅⊢ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} ↔ edge ∈ ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} → edge ∈ ∅node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ ∅ → edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} → edge ∈ ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}⊢ edge ∈ ∅ have hMember : edge ∈ insert (output, input) graph.portEdges ∧ edge.1 = candidate := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ (graph.contract output input hOutputExposed hInputExposed).PortLinear All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = candidate⊢ edge ∈ ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = candidatehNew:edge = (output, input)⊢ edge ∈ ∅node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = candidatehOld:edge ∈ graph.portEdges⊢ edge ∈ ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = candidatehNew:edge = (output, input)⊢ edge ∈ ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅hEdge:(output, input) ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}hInsert:(output, input) ∈ insert (output, input) graph.portEdgeshSource:(output, input).1 = candidate⊢ (output, input) ∈ ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = candidatehOld:edge ∈ graph.portEdges⊢ edge ∈ ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = candidatehOld:edge ∈ graph.portEdgeshOldFiltered:edge ∈ {edge ∈ graph.portEdges | edge.1 = candidate}⊢ edge ∈ ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = candidatehOld:edge ∈ graph.portEdgeshOldFiltered:edge ∈ ∅⊢ edge ∈ ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ ∅ → edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhOpen:candidate ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ ∅⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhConsumed:candidate ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, input)}⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ ∃ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = {(candidate, input_1)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhConsumed:candidate ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, input)}⊢ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ ∃ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = {(candidate, input_1)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}⊢ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs ∧ ∃ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = {(candidate, input_1)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}⊢ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}⊢ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = {(candidate, oldInput)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}⊢ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedOutputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}⊢ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} = {(candidate, oldInput)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} ↔ edge ∈ {(candidate, oldInput)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} → edge ∈ {(candidate, oldInput)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {(candidate, oldInput)} → edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} → edge ∈ {(candidate, oldInput)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}⊢ edge ∈ {(candidate, oldInput)} have hMember : edge ∈ insert (output, input) graph.portEdges ∧ edge.1 = candidate := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ (graph.contract output input hOutputExposed hInputExposed).PortLinear All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = candidate⊢ edge ∈ {(candidate, oldInput)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = candidatehNew:edge = (output, input)⊢ edge ∈ {(candidate, oldInput)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = candidatehOld:edge ∈ graph.portEdges⊢ edge ∈ {(candidate, oldInput)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = candidatehNew:edge = (output, input)⊢ edge ∈ {(candidate, oldInput)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}hEdge:(output, input) ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}hInsert:(output, input) ∈ insert (output, input) graph.portEdgeshSource:(output, input).1 = candidate⊢ (output, input) ∈ {(candidate, oldInput)} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = candidatehOld:edge ∈ graph.portEdges⊢ edge ∈ {(candidate, oldInput)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = candidatehOld:edge ∈ graph.portEdgeshOldFiltered:edge ∈ {edge ∈ graph.portEdges | edge.1 = candidate}⊢ edge ∈ {(candidate, oldInput)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshSource:edge.1 = candidatehOld:edge ∈ graph.portEdgeshOldFiltered:edge ∈ {(candidate, oldInput)}⊢ edge ∈ {(candidate, oldInput)} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {(candidate, oldInput)} → edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {(candidate, oldInput)}⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} have hEdgeOld : edge ∈ graph.portEdges.filter (fun edge => edge.1 = candidate) := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ (graph.contract output input hOutputExposed hInputExposed).PortLinear node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {(candidate, oldInput)}⊢ edge ∈ {(candidate, oldInput)} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node outputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).outputshSame:¬candidate = outputhNotExposed:candidate ∉ graph.exposedOutputsoldInput:SourcePortInstance node inputPorthOldInput:oldInput ∈ graph.inputshEdges:{edge ∈ graph.portEdges | edge.1 = candidate} = {(candidate, oldInput)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {(candidate, oldInput)}hEdgeOld:edge ∈ {edge ∈ graph.portEdges | edge.1 = candidate}hOld:edge ∈ graph.portEdgeshSource:edge.1 = candidate⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.1 = candidate} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅⊢ ∀ input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).inputs, input_1 ∈ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input_1} = ∅ ∨ input_1 ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ ∃ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input_1} = {(output_1, input_1)} intro candidate node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputs⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ ∃ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = {(output_1, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:candidate = input⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ ∃ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = {(output_1, candidate)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = input⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ ∃ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = {(output_1, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:candidate = input⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ ∃ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = {(output_1, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputs⊢ input ∈ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input} = ∅ ∨ input ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ ∃ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input} = {(output_1, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputs⊢ input ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ ∃ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input} = {(output_1, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputs⊢ input ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputs⊢ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputs⊢ input ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputs⊢ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input} ↔ edge ∈ {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input} → edge ∈ {(output, input)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {(output, input)} → edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input} → edge ∈ {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input}⊢ edge ∈ {(output, input)} have hMember : edge ∈ insert (output, input) graph.portEdges ∧ edge.2 = input := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ (graph.contract output input hOutputExposed hInputExposed).PortLinear All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = input⊢ edge ∈ {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = inputhNew:edge = (output, input)⊢ edge ∈ {(output, input)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = inputhOld:edge ∈ graph.portEdges⊢ edge ∈ {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = inputhNew:edge = (output, input)⊢ edge ∈ {(output, input)} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = inputhOld:edge ∈ graph.portEdges⊢ edge ∈ {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = inputhOld:edge ∈ graph.portEdgeshOldFiltered:edge ∈ {edge ∈ graph.portEdges | edge.2 = input}⊢ edge ∈ {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = inputhOld:edge ∈ graph.portEdgeshOldFiltered:edge ∈ ∅⊢ edge ∈ {(output, input)} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {(output, input)} → edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputsedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {(output, input)}⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input} have hEq : edge = (output, input) := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ (graph.contract output input hOutputExposed hInputExposed).PortLinear All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅hCandidate:input ∈ (graph.contract output input hOutputExposed hInputExposed).inputshEdge:(output, input) ∈ {(output, input)}⊢ (output, input) ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = input} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = input⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ ∃ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = {(output_1, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOldLinear:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅ ∨ candidate ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = candidate} = {(output, candidate)}⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ ∃ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = {(output_1, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ ∃ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = {(output_1, candidate)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhProduced:candidate ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = candidate} = {(output, candidate)}⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ ∃ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = {(output_1, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ ∃ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = {(output_1, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedInputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅⊢ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedInputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅⊢ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} ↔ edge ∈ ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} → edge ∈ ∅node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ ∅ → edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} → edge ∈ ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}⊢ edge ∈ ∅ have hMember : edge ∈ insert (output, input) graph.portEdges ∧ edge.2 = candidate := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ (graph.contract output input hOutputExposed hInputExposed).PortLinear All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = candidate⊢ edge ∈ ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = candidatehNew:edge = (output, input)⊢ edge ∈ ∅node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = candidatehOld:edge ∈ graph.portEdges⊢ edge ∈ ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = candidatehNew:edge = (output, input)⊢ edge ∈ ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅hEdge:(output, input) ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}hInsert:(output, input) ∈ insert (output, input) graph.portEdgeshTarget:(output, input).2 = candidate⊢ (output, input) ∈ ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = candidatehOld:edge ∈ graph.portEdges⊢ edge ∈ ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = candidatehOld:edge ∈ graph.portEdgeshOldFiltered:edge ∈ {edge ∈ graph.portEdges | edge.2 = candidate}⊢ edge ∈ ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = candidatehOld:edge ∈ graph.portEdgeshOldFiltered:edge ∈ ∅⊢ edge ∈ ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ ∅ → edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhOpen:candidate ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = candidate} = ∅edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ ∅⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhProduced:candidate ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = candidate} = {(output, candidate)}⊢ candidate ∈ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = ∅ ∨ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ ∃ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = {(output_1, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhProduced:candidate ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = candidate} = {(output, candidate)}⊢ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ ∃ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = {(output_1, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}⊢ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs ∧ ∃ output_1 ∈ (graph.contract output input hOutputExposed hInputExposed).outputs, {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = {(output_1, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}⊢ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}⊢ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = {(oldOutput, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}⊢ candidate ∉ (graph.contract output input hOutputExposed hInputExposed).exposedInputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}⊢ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} = {(oldOutput, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} ↔ edge ∈ {(oldOutput, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} → edge ∈ {(oldOutput, candidate)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {(oldOutput, candidate)} → edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} → edge ∈ {(oldOutput, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}⊢ edge ∈ {(oldOutput, candidate)} have hMember : edge ∈ insert (output, input) graph.portEdges ∧ edge.2 = candidate := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ (graph.contract output input hOutputExposed hInputExposed).PortLinear All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = candidate⊢ edge ∈ {(oldOutput, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = candidatehNew:edge = (output, input)⊢ edge ∈ {(oldOutput, candidate)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = candidatehOld:edge ∈ graph.portEdges⊢ edge ∈ {(oldOutput, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = candidatehNew:edge = (output, input)⊢ edge ∈ {(oldOutput, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}hEdge:(output, input) ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}hInsert:(output, input) ∈ insert (output, input) graph.portEdgeshTarget:(output, input).2 = candidate⊢ (output, input) ∈ {(oldOutput, candidate)} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = candidatehOld:edge ∈ graph.portEdges⊢ edge ∈ {(oldOutput, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = candidatehOld:edge ∈ graph.portEdgeshOldFiltered:edge ∈ {edge ∈ graph.portEdges | edge.2 = candidate}⊢ edge ∈ {(oldOutput, candidate)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate}hInsert:edge ∈ insert (output, input) graph.portEdgeshTarget:edge.2 = candidatehOld:edge ∈ graph.portEdgeshOldFiltered:edge ∈ {(oldOutput, candidate)}⊢ edge ∈ {(oldOutput, candidate)} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPort⊢ edge ∈ {(oldOutput, candidate)} → edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {(oldOutput, candidate)}⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} have hEdgeOld : edge ∈ graph.portEdges.filter (fun edge => edge.2 = candidate) := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputs⊢ (graph.contract output input hOutputExposed hInputExposed).PortLinear node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {(oldOutput, candidate)}⊢ edge ∈ {(oldOutput, candidate)} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinearoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputshOutputMem:output ∈ graph.outputshInputMem:input ∈ graph.inputshOutputOpen:output ∈ graph.exposedOutputs ∧ {edge ∈ graph.portEdges | edge.1 = output} = ∅ ∨ output ∉ graph.exposedOutputs ∧ ∃ input ∈ graph.inputs, {edge ∈ graph.portEdges | edge.1 = output} = {(output, input)}hInputOpen:input ∈ graph.exposedInputs ∧ {edge ∈ graph.portEdges | edge.2 = input} = ∅ ∨ input ∉ graph.exposedInputs ∧ ∃ output ∈ graph.outputs, {edge ∈ graph.portEdges | edge.2 = input} = {(output, input)}hOutputNoEdges:{edge ∈ graph.portEdges | edge.1 = output} = ∅hInputNoEdges:{edge ∈ graph.portEdges | edge.2 = input} = ∅candidate:SourcePortInstance node inputPorthCandidate:candidate ∈ (graph.contract output input hOutputExposed hInputExposed).inputshSame:¬candidate = inputhNotExposed:candidate ∉ graph.exposedInputsoldOutput:SourcePortInstance node outputPorthOldOutput:oldOutput ∈ graph.outputshEdges:{edge ∈ graph.portEdges | edge.2 = candidate} = {(oldOutput, candidate)}edge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ {(oldOutput, candidate)}hEdgeOld:edge ∈ {edge ∈ graph.portEdges | edge.2 = candidate}hOld:edge ∈ graph.portEdgeshTarget:edge.2 = candidate⊢ edge ∈ {edge ∈ (graph.contract output input hOutputExposed hInputExposed).portEdges | edge.2 = candidate} All goals completed! 🐙

Certified Bulk Contraction

BulkContract start finish is a sequence of certified single-pair contractions.

This models the preservation side of bulk => contraction after deterministic matching has already chosen the pairs and ordered the certified steps. The raw compatibility/match-count algorithm and static-error cases remain compiler-admission obligations.

ADR 0047 treats the selected matches as one simultaneous boundary contraction. This proof carrier records them as an ordered trace only so preservation can proceed by induction over the already certified single-pair contraction theorem. The trace order is not intended to carry source semantics; a future bulkContract_permutation_invariant lemma should make the permutation invariance explicit.

inductive BulkContract : LinearPortGraph node outputPort inputPort → LinearPortGraph node outputPort inputPort → Type where | done (graph : LinearPortGraph node outputPort inputPort) : BulkContract graph graph | step (graph : LinearPortGraph node outputPort inputPort) (output : SourcePortInstance node outputPort) (input : SourcePortInstance node inputPort) (hOutputExposed : output ∈ graph.exposedOutputs) (hInputExposed : input ∈ graph.exposedInputs) {finish : LinearPortGraph node outputPort inputPort} (tail : BulkContract (graph.contract output input hOutputExposed hInputExposed) finish) : BulkContract graph finish

Certified bulk contraction preserves source port linearity.

theorem bulkContract_preserves_portLinear {start finish : LinearPortGraph node outputPort inputPort} (hBulk : BulkContract start finish) (hLinear : start.PortLinear) : finish.PortLinear := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortstart:LinearPortGraph node outputPort inputPortfinish:LinearPortGraph node outputPort inputPorthBulk:start.BulkContract finishhLinear:start.PortLinear⊢ finish.PortLinear induction hBulk with node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortstart:LinearPortGraph node outputPort inputPortfinish:LinearPortGraph node outputPort inputPortgraph:LinearPortGraph node outputPort inputPorthLinear:graph.PortLinear⊢ graph.PortLinear All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortstart:LinearPortGraph node outputPort inputPortfinish:LinearPortGraph node outputPort inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsfinish✝:LinearPortGraph node outputPort inputPorttail:(graph.contract output input hOutputExposed hInputExposed).BulkContract finish✝ih:(graph.contract output input hOutputExposed hInputExposed).PortLinear → finish✝.PortLinearhLinear:graph.PortLinear⊢ finish✝.PortLinear All goals completed! 🐙

Node-level relation edges inserted by a certified bulk contraction trace.

def BulkContract.loweredEdges : {start finish : LinearPortGraph node outputPort inputPort} → BulkContract start finish → Finset (node × node) | _, _, BulkContract.done _ => ∅ | _, _, BulkContract.step _ output input _ _ tail => insert (output.node, input.node) (BulkContract.loweredEdges tail)

Forgetting ports after certified bulk contraction inserts some finite set of node edges.

The inserted relation edges are projected from the certified contraction trace. After lowering, port identity is forgotten, but the node-level edge set remains tied to the source proof object.

theorem forgetPorts_bulkContract {start finish : LinearPortGraph node outputPort inputPort} (hBulk : BulkContract start finish) : finish.forgetPorts = { vertices := start.forgetPorts.vertices edges := start.forgetPorts.edges ∪ hBulk.loweredEdges } := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortstart:LinearPortGraph node outputPort inputPortfinish:LinearPortGraph node outputPort inputPorthBulk:start.BulkContract finish⊢ finish.forgetPorts = { vertices := start.forgetPorts.vertices, edges := start.forgetPorts.edges ∪ hBulk.loweredEdges } induction hBulk with node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortstart:LinearPortGraph node outputPort inputPortfinish:LinearPortGraph node outputPort inputPortgraph:LinearPortGraph node outputPort inputPort⊢ graph.forgetPorts = { vertices := graph.forgetPorts.vertices, edges := graph.forgetPorts.edges ∪ (BulkContract.done graph).loweredEdges } node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortstart:LinearPortGraph node outputPort inputPortfinish:LinearPortGraph node outputPort inputPortgraph:LinearPortGraph node outputPort inputPortedge:node⊢ edge ∈ graph.forgetPorts.vertices ↔ edge ∈ { vertices := graph.forgetPorts.vertices, edges := graph.forgetPorts.edges ∪ (BulkContract.done graph).loweredEdges }.verticesnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortstart:LinearPortGraph node outputPort inputPortfinish:LinearPortGraph node outputPort inputPortgraph:LinearPortGraph node outputPort inputPortedge:node × node⊢ edge ∈ graph.forgetPorts.edges ↔ edge ∈ { vertices := graph.forgetPorts.vertices, edges := graph.forgetPorts.edges ∪ (BulkContract.done graph).loweredEdges }.edges node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortstart:LinearPortGraph node outputPort inputPortfinish:LinearPortGraph node outputPort inputPortgraph:LinearPortGraph node outputPort inputPortedge:node⊢ edge ∈ graph.forgetPorts.vertices ↔ edge ∈ { vertices := graph.forgetPorts.vertices, edges := graph.forgetPorts.edges ∪ (BulkContract.done graph).loweredEdges }.verticesnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortstart:LinearPortGraph node outputPort inputPortfinish:LinearPortGraph node outputPort inputPortgraph:LinearPortGraph node outputPort inputPortedge:node × node⊢ edge ∈ graph.forgetPorts.edges ↔ edge ∈ { vertices := graph.forgetPorts.vertices, edges := graph.forgetPorts.edges ∪ (BulkContract.done graph).loweredEdges }.edges All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortstart:LinearPortGraph node outputPort inputPortfinish:LinearPortGraph node outputPort inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsfinish✝:LinearPortGraph node outputPort inputPorttail:(graph.contract output input hOutputExposed hInputExposed).BulkContract finish✝ih:finish✝.forgetPorts = { vertices := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.vertices, edges := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.edges ∪ tail.loweredEdges }⊢ finish✝.forgetPorts = { vertices := graph.forgetPorts.vertices, edges := graph.forgetPorts.edges ∪ (BulkContract.step graph output input hOutputExposed hInputExposed tail).loweredEdges } node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortstart:LinearPortGraph node outputPort inputPortfinish:LinearPortGraph node outputPort inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsfinish✝:LinearPortGraph node outputPort inputPorttail:(graph.contract output input hOutputExposed hInputExposed).BulkContract finish✝ih:finish✝.forgetPorts = { vertices := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.vertices, edges := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.edges ∪ tail.loweredEdges }⊢ { vertices := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.vertices, edges := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.edges ∪ tail.loweredEdges } = { vertices := graph.forgetPorts.vertices, edges := graph.forgetPorts.edges ∪ (BulkContract.step graph output input hOutputExposed hInputExposed tail).loweredEdges } node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortstart:LinearPortGraph node outputPort inputPortfinish:LinearPortGraph node outputPort inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsfinish✝:LinearPortGraph node outputPort inputPorttail:(graph.contract output input hOutputExposed hInputExposed).BulkContract finish✝ih:finish✝.forgetPorts = { vertices := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.vertices, edges := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.edges ∪ tail.loweredEdges }edge:node⊢ edge ∈ { vertices := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.vertices, edges := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.edges ∪ tail.loweredEdges }.vertices ↔ edge ∈ { vertices := graph.forgetPorts.vertices, edges := graph.forgetPorts.edges ∪ (BulkContract.step graph output input hOutputExposed hInputExposed tail).loweredEdges }.verticesnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortstart:LinearPortGraph node outputPort inputPortfinish:LinearPortGraph node outputPort inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsfinish✝:LinearPortGraph node outputPort inputPorttail:(graph.contract output input hOutputExposed hInputExposed).BulkContract finish✝ih:finish✝.forgetPorts = { vertices := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.vertices, edges := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.edges ∪ tail.loweredEdges }edge:node × node⊢ edge ∈ { vertices := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.vertices, edges := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.edges ∪ tail.loweredEdges }.edges ↔ edge ∈ { vertices := graph.forgetPorts.vertices, edges := graph.forgetPorts.edges ∪ (BulkContract.step graph output input hOutputExposed hInputExposed tail).loweredEdges }.edges node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortstart:LinearPortGraph node outputPort inputPortfinish:LinearPortGraph node outputPort inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsfinish✝:LinearPortGraph node outputPort inputPorttail:(graph.contract output input hOutputExposed hInputExposed).BulkContract finish✝ih:finish✝.forgetPorts = { vertices := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.vertices, edges := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.edges ∪ tail.loweredEdges }edge:node⊢ edge ∈ { vertices := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.vertices, edges := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.edges ∪ tail.loweredEdges }.vertices ↔ edge ∈ { vertices := graph.forgetPorts.vertices, edges := graph.forgetPorts.edges ∪ (BulkContract.step graph output input hOutputExposed hInputExposed tail).loweredEdges }.verticesnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortstart:LinearPortGraph node outputPort inputPortfinish:LinearPortGraph node outputPort inputPortgraph:LinearPortGraph node outputPort inputPortoutput:SourcePortInstance node outputPortinput:SourcePortInstance node inputPorthOutputExposed:output ∈ graph.exposedOutputshInputExposed:input ∈ graph.exposedInputsfinish✝:LinearPortGraph node outputPort inputPorttail:(graph.contract output input hOutputExposed hInputExposed).BulkContract finish✝ih:finish✝.forgetPorts = { vertices := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.vertices, edges := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.edges ∪ tail.loweredEdges }edge:node × node⊢ edge ∈ { vertices := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.vertices, edges := (graph.contract output input hOutputExposed hInputExposed).forgetPorts.edges ∪ tail.loweredEdges }.edges ↔ edge ∈ { vertices := graph.forgetPorts.vertices, edges := graph.forgetPorts.edges ∪ (BulkContract.step graph output input hOutputExposed hInputExposed tail).loweredEdges }.edges All goals completed! 🐙

openNodePorts creates a source graph whose node ports are all open frontier resources.

This is the primitive node_ports object in the linear source algebra. It does not add edges or perform contraction; later operations must consume exposed endpoints explicitly.

def openNodePorts (nodes : Finset node) (outputs : Finset (SourcePortInstance node outputPort)) (inputs : Finset (SourcePortInstance node inputPort)) (hOutputNodes : ∀ output, output ∈ outputs → output.node ∈ nodes) (hInputNodes : ∀ input, input ∈ inputs → input.node ∈ nodes) : LinearPortGraph node outputPort inputPort where nodes := nodes outputs := outputs inputs := inputs exposedOutputs := outputs exposedInputs := inputs portEdges := ∅ output_nodes := hOutputNodes input_nodes := hInputNodes exposedOutput_mem := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodes⊢ ∀ output ∈ outputs, output ∈ outputs intro output node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodesoutput:SourcePortInstance node outputPorthOutput:output ∈ outputs⊢ output ∈ outputs All goals completed! 🐙 exposedInput_mem := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodes⊢ ∀ input ∈ inputs, input ∈ inputs intro input node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodesinput:SourcePortInstance node inputPorthInput:input ∈ inputs⊢ input ∈ inputs All goals completed! 🐙 edge_output_mem := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodes⊢ ∀ edge ∈ ∅, edge.1 ∈ outputs intro edge node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodesedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ ∅⊢ edge.1 ∈ outputs All goals completed! 🐙 edge_input_mem := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodes⊢ ∀ edge ∈ ∅, edge.2 ∈ inputs intro edge node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodesedge:SourcePortInstance node outputPort × SourcePortInstance node inputPorthEdge:edge ∈ ∅⊢ edge.2 ∈ inputs All goals completed! 🐙

Open node-port resources are source-linear before any operation consumes them.

theorem openNodePorts_portLinear (nodes : Finset node) (outputs : Finset (SourcePortInstance node outputPort)) (inputs : Finset (SourcePortInstance node inputPort)) (hOutputNodes : ∀ output, output ∈ outputs → output.node ∈ nodes) (hInputNodes : ∀ input, input ∈ inputs → input.node ∈ nodes) : (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).PortLinear := node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodes⊢ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).PortLinear node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodes⊢ ∀ output ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).outputs, output ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedOutputs ∧ {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.1 = output} = ∅ ∨ output ∉ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedOutputs ∧ ∃ input ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).inputs, {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.1 = output} = {(output, input)}node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodes⊢ ∀ input ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).inputs, input ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedInputs ∧ {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.2 = input} = ∅ ∨ input ∉ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedInputs ∧ ∃ output ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).outputs, {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodes⊢ ∀ output ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).outputs, output ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedOutputs ∧ {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.1 = output} = ∅ ∨ output ∉ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedOutputs ∧ ∃ input ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).inputs, {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.1 = output} = {(output, input)} intro output node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodesoutput:SourcePortInstance node outputPorthOutput:output ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).outputs⊢ output ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedOutputs ∧ {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.1 = output} = ∅ ∨ output ∉ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedOutputs ∧ ∃ input ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).inputs, {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.1 = output} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodesoutput:SourcePortInstance node outputPorthOutput:output ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).outputs⊢ output ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedOutputs ∧ {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.1 = output} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodesoutput:SourcePortInstance node outputPorthOutput:output ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).outputs⊢ output ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedOutputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodesoutput:SourcePortInstance node outputPorthOutput:output ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).outputs⊢ {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.1 = output} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodesoutput:SourcePortInstance node outputPorthOutput:output ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).outputs⊢ output ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedOutputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodesoutput:SourcePortInstance node outputPorthOutput:output ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).outputs⊢ {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.1 = output} = ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodes⊢ ∀ input ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).inputs, input ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedInputs ∧ {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.2 = input} = ∅ ∨ input ∉ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedInputs ∧ ∃ output ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).outputs, {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.2 = input} = {(output, input)} intro input node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodesinput:SourcePortInstance node inputPorthInput:input ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).inputs⊢ input ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedInputs ∧ {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.2 = input} = ∅ ∨ input ∉ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedInputs ∧ ∃ output ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).outputs, {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.2 = input} = {(output, input)} node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodesinput:SourcePortInstance node inputPorthInput:input ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).inputs⊢ input ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedInputs ∧ {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.2 = input} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodesinput:SourcePortInstance node inputPorthInput:input ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).inputs⊢ input ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedInputsnode:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodesinput:SourcePortInstance node inputPorthInput:input ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).inputs⊢ {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.2 = input} = ∅ node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodesinput:SourcePortInstance node inputPorthInput:input ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).inputs⊢ input ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).exposedInputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeinst✝²:DecidableEq nodeinst✝¹:DecidableEq outputPortinst✝:DecidableEq inputPortnodes:Finset nodeoutputs:Finset (SourcePortInstance node outputPort)inputs:Finset (SourcePortInstance node inputPort)hOutputNodes:∀ output ∈ outputs, output.node ∈ nodeshInputNodes:∀ input ∈ inputs, input.node ∈ nodesinput:SourcePortInstance node inputPorthInput:input ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).inputs⊢ {edge ∈ (openNodePorts nodes outputs inputs hOutputNodes hInputNodes).portEdges | edge.2 = input} = ∅ All goals completed! 🐙

LinearPortObject packages a source port graph with its linear-resource proof.

The source algebra works over these objects, not over raw graph syntax. This is the proof-level version of "{operations, node_ports}" as the linear interface.

structure LinearPortObject (node outputPort inputPort : Type) [DecidableEq node] [DecidableEq outputPort] [DecidableEq inputPort] where

Source port graph carried by this linear object.

graph : LinearPortGraph node outputPort inputPort

The graph satisfies the source endpoint linearity rule.

linear : graph.PortLinearnamespace LinearPortObject

Construct a linear object from open node-port resources.

def nodePorts (nodes : Finset node) (outputs : Finset (SourcePortInstance node outputPort)) (inputs : Finset (SourcePortInstance node inputPort)) (hOutputNodes : ∀ output, output ∈ outputs → output.node ∈ nodes) (hInputNodes : ∀ input, input ∈ inputs → input.node ∈ nodes) : LinearPortObject node outputPort inputPort where graph := openNodePorts nodes outputs inputs hOutputNodes hInputNodes linear := openNodePorts_portLinear nodes outputs inputs hOutputNodes hInputNodes

Certified overlay is a linear algebra operation when endpoint resources are disjoint.

def overlay (left right : LinearPortObject node outputPort inputPort) (hDisjoint : DomainDisjoint left.graph right.graph) : LinearPortObject node outputPort inputPort where graph := LinearPortGraph.overlay left.graph right.graph linear := overlay_preserves_portLinear left.graph right.graph left.linear right.linear hDisjointend LinearPortObject

A source operation is certified for linearity when it returns a linear proof object.

This is a proof-object interface, not an executable elaboration theorem. Raw syntax such as => becomes part of this layer only after the compiler supplies the corresponding certificate.

structure LinearPortOperation (node outputPort inputPort : Type) [DecidableEq node] [DecidableEq outputPort] [DecidableEq inputPort] where

Execute the certified operation on a linear source object.

apply : LinearPortObject node outputPort inputPort → LinearPortObject node outputPort inputPortnamespace LinearPortOperation

Sequential composition of certified linear source operations.

def thenOp (first second : LinearPortOperation node outputPort inputPort) : LinearPortOperation node outputPort inputPort where apply := fun object => second.apply (first.apply object)

Running a certified operation exposes the returned object's source-linearity proof.

theorem apply_result_portLinear (operation : LinearPortOperation node outputPort inputPort) (object : LinearPortObject node outputPort inputPort) : (operation.apply object).graph.PortLinear := (operation.apply object).linear

Sequential composition exposes the returned object's source-linearity proof.

theorem thenOp_result_portLinear (first second : LinearPortOperation node outputPort inputPort) (object : LinearPortObject node outputPort inputPort) : ((first.thenOp second).apply object).graph.PortLinear := ((first.thenOp second).apply object).linearend LinearPortOperation

LinearPortSystem packages a certified source object after source elaboration.

This is intentionally not raw Wire or Mokhov syntax. It is the interface that compiler elaboration must target before claiming source frontier linearity.

structure LinearPortSystem (node outputPort inputPort : Type) [DecidableEq node] [DecidableEq outputPort] [DecidableEq inputPort] where

Certified linear object produced by the source algebra.

object : LinearPortObject node outputPort inputPortnamespace LinearPortSystem

The primitive node_ports generator for the source linear algebra.

def nodePorts (nodes : Finset node) (outputs : Finset (SourcePortInstance node outputPort)) (inputs : Finset (SourcePortInstance node inputPort)) (hOutputNodes : ∀ output, output ∈ outputs → output.node ∈ nodes) (hInputNodes : ∀ input, input ∈ inputs → input.node ∈ nodes) : LinearPortSystem node outputPort inputPort where object := LinearPortObject.nodePorts nodes outputs inputs hOutputNodes hInputNodes

Certified overlay is one operation of the certified source system layer.

def overlay (left right : LinearPortSystem node outputPort inputPort) (hDisjoint : DomainDisjoint left.object.graph right.object.graph) : LinearPortSystem node outputPort inputPort where object := LinearPortObject.overlay left.object right.object hDisjoint

Apply a certified operation inside the certified source system layer.

def operation (operation : LinearPortOperation node outputPort inputPort) (input : LinearPortSystem node outputPort inputPort) : LinearPortSystem node outputPort inputPort where object := operation.apply input.object

A certified source system exposes its bundled source-linearity proof.

theorem certified_portLinear (system : LinearPortSystem node outputPort inputPort) : system.object.graph.PortLinear := system.object.linearend LinearPortSystemend LinearPortGraph

Port Instances And Uses

ActualizedPortInstance identifies one named port on one actualized node.

structure ActualizedPortInstance (node port : Type) where

Actualized node that owns this port instance.

node : node

Port label or proof-side port identity on that node.

port : port deriving DecidableEq, Repr

OutputPortUse is one concrete consumer for one output port instance.

The terminal payload abstracts over egress, sink, and exported-boundary discharges. Port linearity only needs to know that terminal discharge consumes the output once; the terminal's operational kind is a later correspondence detail.

inductive OutputPortUse (input terminal : Type) : Type where | edge (input : input) | terminalDischarge (terminal : terminal) deriving DecidableEq, Repr

Actualized Port Graphs

ActualizedPortGraph records port consumers and producers for a closed graph.

structure ActualizedPortGraph (node outputPort inputPort terminal : Type) [DecidableEq node] [DecidableEq outputPort] [DecidableEq inputPort] [DecidableEq terminal] where

Output port instances that must be accounted for.

outputs : Finset (ActualizedPortInstance node outputPort)

Input port instances that must be accounted for.

inputs : Finset (ActualizedPortInstance node inputPort)

Downstream input consumers for each output port instance.

edgeConsumers : ActualizedPortInstance node outputPort → Finset (ActualizedPortInstance node inputPort)

Terminal discharges for each output port instance.

terminalDischarges : ActualizedPortInstance node outputPort → Finset terminal

Upstream output producers for each input port instance.

inputProducers : ActualizedPortInstance node inputPort → Finset (ActualizedPortInstance node outputPort)namespace ActualizedPortGraphvariable {node outputPort inputPort terminal : Type}variable [DecidableEq node]variable [DecidableEq outputPort]variable [DecidableEq inputPort]variable [DecidableEq terminal]

An output has exactly one edge consumer or exactly one terminal discharge.

def OutputConsumedExactlyOnce (graph : ActualizedPortGraph node outputPort inputPort terminal) (output : ActualizedPortInstance node outputPort) : Prop := (∃ input, input ∈ graph.inputs ∧ graph.edgeConsumers output = {input} ∧ graph.terminalDischarges output = ∅) ∨ ∃ terminal, graph.edgeConsumers output = ∅ ∧ graph.terminalDischarges output = {terminal}

An input has exactly one edge producer.

def InputProducedExactlyOnce (graph : ActualizedPortGraph node outputPort inputPort terminal) (input : ActualizedPortInstance node inputPort) : Prop := ∃ output, output ∈ graph.outputs ∧ graph.inputProducers input = {output} ∧ graph.edgeConsumers output = {input}

ClosedOutputLinear graph is the output-consumer side of closed port use.

def ClosedOutputLinear (graph : ActualizedPortGraph node outputPort inputPort terminal) : Prop := ∀ output, output ∈ graph.outputs → graph.OutputConsumedExactlyOnce output

ClosedInputLinear graph is the input-producer side of closed port use.

def ClosedInputLinear (graph : ActualizedPortGraph node outputPort inputPort terminal) : Prop := ∀ input, input ∈ graph.inputs → graph.InputProducedExactlyOnce input

ClosedPortLinear graph is Paper 5's exact-once rule for closed actualized port use.

def ClosedPortLinear (graph : ActualizedPortGraph node outputPort inputPort terminal) : Prop := graph.ClosedOutputLinear ∧ graph.ClosedInputLinear

Output domains are disjoint when no output port instance occurs in both graphs.

def OutputDisjoint (left right : ActualizedPortGraph node outputPort inputPort terminal) : Prop := ∀ output, output ∈ left.outputs → output ∈ right.outputs → False

Input domains are disjoint when no input port instance occurs in both graphs.

def InputDisjoint (left right : ActualizedPortGraph node outputPort inputPort terminal) : Prop := ∀ input, input ∈ left.inputs → input ∈ right.inputs → False

Port domains are disjoint when both input and output port domains are disjoint.

def DomainDisjoint (left right : ActualizedPortGraph node outputPort inputPort terminal) : Prop := OutputDisjoint left right ∧ InputDisjoint left right

overlay left right combines disjoint actualized port-use graphs.

def overlay (left right : ActualizedPortGraph node outputPort inputPort terminal) : ActualizedPortGraph node outputPort inputPort terminal where outputs := left.outputs ∪ right.outputs inputs := left.inputs ∪ right.inputs edgeConsumers := fun output => if output ∈ left.outputs then left.edgeConsumers output else right.edgeConsumers output terminalDischarges := fun output => if output ∈ left.outputs then left.terminalDischarges output else right.terminalDischarges output inputProducers := fun input => if input ∈ left.inputs then left.inputProducers input else right.inputProducers input

Closed port linearity is preserved by overlaying disjoint port domains.

theorem overlay_preserves_closedPortLinearity (left right : ActualizedPortGraph node outputPort inputPort terminal) (hLeft : left.ClosedPortLinear) (hRight : right.ClosedPortLinear) (hDisjoint : DomainDisjoint left right) : (overlay left right).ClosedPortLinear := node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint right⊢ (left.overlay right).ClosedPortLinear node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint right⊢ (left.overlay right).ClosedOutputLinearnode:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint right⊢ (left.overlay right).ClosedInputLinear node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint right⊢ (left.overlay right).ClosedOutputLinear intro output node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputs⊢ (left.overlay right).OutputConsumedExactlyOnce output node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint right⊢ (left.overlay right).OutputConsumedExactlyOnce output have hUnion : output ∈ left.outputs ∪ right.outputs := node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint right⊢ (left.overlay right).ClosedPortLinear All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshEither:output ∈ left.outputs ∨ output ∈ right.outputs⊢ (left.overlay right).OutputConsumedExactlyOnce output cases hEither with node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputs⊢ (left.overlay right).OutputConsumedExactlyOnce output node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputshLinear:left.OutputConsumedExactlyOnce output⊢ (left.overlay right).OutputConsumedExactlyOnce output cases hLinear with node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputshEdge:∃ input ∈ left.inputs, left.edgeConsumers output = {input} ∧ left.terminalDischarges output = ∅⊢ (left.overlay right).OutputConsumedExactlyOnce output node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputsinput:ActualizedPortInstance node inputPorthInput:input ∈ left.inputshEdges:left.edgeConsumers output = {input}hTerminals:left.terminalDischarges output = ∅⊢ (left.overlay right).OutputConsumedExactlyOnce output node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputsinput:ActualizedPortInstance node inputPorthInput:input ∈ left.inputshEdges:left.edgeConsumers output = {input}hTerminals:left.terminalDischarges output = ∅⊢ ∃ input ∈ (left.overlay right).inputs, (left.overlay right).edgeConsumers output = {input} ∧ (left.overlay right).terminalDischarges output = ∅ node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputsinput:ActualizedPortInstance node inputPorthInput:input ∈ left.inputshEdges:left.edgeConsumers output = {input}hTerminals:left.terminalDischarges output = ∅⊢ input ∈ (left.overlay right).inputsnode:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputsinput:ActualizedPortInstance node inputPorthInput:input ∈ left.inputshEdges:left.edgeConsumers output = {input}hTerminals:left.terminalDischarges output = ∅⊢ (left.overlay right).edgeConsumers output = {input}node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputsinput:ActualizedPortInstance node inputPorthInput:input ∈ left.inputshEdges:left.edgeConsumers output = {input}hTerminals:left.terminalDischarges output = ∅⊢ (left.overlay right).terminalDischarges output = ∅ node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputsinput:ActualizedPortInstance node inputPorthInput:input ∈ left.inputshEdges:left.edgeConsumers output = {input}hTerminals:left.terminalDischarges output = ∅⊢ input ∈ (left.overlay right).inputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputsinput:ActualizedPortInstance node inputPorthInput:input ∈ left.inputshEdges:left.edgeConsumers output = {input}hTerminals:left.terminalDischarges output = ∅⊢ (left.overlay right).edgeConsumers output = {input} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputsinput:ActualizedPortInstance node inputPorthInput:input ∈ left.inputshEdges:left.edgeConsumers output = {input}hTerminals:left.terminalDischarges output = ∅⊢ (left.overlay right).terminalDischarges output = ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputshTerminal:∃ terminal_1, left.edgeConsumers output = ∅ ∧ left.terminalDischarges output = {terminal_1}⊢ (left.overlay right).OutputConsumedExactlyOnce output node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputsterminal:terminal✝hEdges:left.edgeConsumers output = ∅hTerminals:left.terminalDischarges output = {terminal}⊢ (left.overlay right).OutputConsumedExactlyOnce output node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputsterminal:terminal✝hEdges:left.edgeConsumers output = ∅hTerminals:left.terminalDischarges output = {terminal}⊢ ∃ terminal, (left.overlay right).edgeConsumers output = ∅ ∧ (left.overlay right).terminalDischarges output = {terminal} node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputsterminal:terminal✝hEdges:left.edgeConsumers output = ∅hTerminals:left.terminalDischarges output = {terminal}⊢ (left.overlay right).edgeConsumers output = ∅node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputsterminal:terminal✝hEdges:left.edgeConsumers output = ∅hTerminals:left.terminalDischarges output = {terminal}⊢ (left.overlay right).terminalDischarges output = {terminal} node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputsterminal:terminal✝hEdges:left.edgeConsumers output = ∅hTerminals:left.terminalDischarges output = {terminal}⊢ (left.overlay right).edgeConsumers output = ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshLeftOutput:output ∈ left.outputsterminal:terminal✝hEdges:left.edgeConsumers output = ∅hTerminals:left.terminalDischarges output = {terminal}⊢ (left.overlay right).terminalDischarges output = {terminal} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputs⊢ (left.overlay right).OutputConsumedExactlyOnce output have hNotLeft : output ∉ left.outputs := node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint right⊢ (left.overlay right).ClosedPortLinear node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshLeftOutput:output ∈ left.outputs⊢ False All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshLinear:right.OutputConsumedExactlyOnce output⊢ (left.overlay right).OutputConsumedExactlyOnce output cases hLinear with node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshEdge:∃ input ∈ right.inputs, right.edgeConsumers output = {input} ∧ right.terminalDischarges output = ∅⊢ (left.overlay right).OutputConsumedExactlyOnce output node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputsinput:ActualizedPortInstance node inputPorthInput:input ∈ right.inputshEdges:right.edgeConsumers output = {input}hTerminals:right.terminalDischarges output = ∅⊢ (left.overlay right).OutputConsumedExactlyOnce output node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputsinput:ActualizedPortInstance node inputPorthInput:input ∈ right.inputshEdges:right.edgeConsumers output = {input}hTerminals:right.terminalDischarges output = ∅⊢ ∃ input ∈ (left.overlay right).inputs, (left.overlay right).edgeConsumers output = {input} ∧ (left.overlay right).terminalDischarges output = ∅ node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputsinput:ActualizedPortInstance node inputPorthInput:input ∈ right.inputshEdges:right.edgeConsumers output = {input}hTerminals:right.terminalDischarges output = ∅⊢ input ∈ (left.overlay right).inputsnode:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputsinput:ActualizedPortInstance node inputPorthInput:input ∈ right.inputshEdges:right.edgeConsumers output = {input}hTerminals:right.terminalDischarges output = ∅⊢ (left.overlay right).edgeConsumers output = {input}node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputsinput:ActualizedPortInstance node inputPorthInput:input ∈ right.inputshEdges:right.edgeConsumers output = {input}hTerminals:right.terminalDischarges output = ∅⊢ (left.overlay right).terminalDischarges output = ∅ node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputsinput:ActualizedPortInstance node inputPorthInput:input ∈ right.inputshEdges:right.edgeConsumers output = {input}hTerminals:right.terminalDischarges output = ∅⊢ input ∈ (left.overlay right).inputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputsinput:ActualizedPortInstance node inputPorthInput:input ∈ right.inputshEdges:right.edgeConsumers output = {input}hTerminals:right.terminalDischarges output = ∅⊢ (left.overlay right).edgeConsumers output = {input} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputsinput:ActualizedPortInstance node inputPorthInput:input ∈ right.inputshEdges:right.edgeConsumers output = {input}hTerminals:right.terminalDischarges output = ∅⊢ (left.overlay right).terminalDischarges output = ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputshTerminal:∃ terminal_1, right.edgeConsumers output = ∅ ∧ right.terminalDischarges output = {terminal_1}⊢ (left.overlay right).OutputConsumedExactlyOnce output node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputsterminal:terminal✝hEdges:right.edgeConsumers output = ∅hTerminals:right.terminalDischarges output = {terminal}⊢ (left.overlay right).OutputConsumedExactlyOnce output node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputsterminal:terminal✝hEdges:right.edgeConsumers output = ∅hTerminals:right.terminalDischarges output = {terminal}⊢ ∃ terminal, (left.overlay right).edgeConsumers output = ∅ ∧ (left.overlay right).terminalDischarges output = {terminal} node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputsterminal:terminal✝hEdges:right.edgeConsumers output = ∅hTerminals:right.terminalDischarges output = {terminal}⊢ (left.overlay right).edgeConsumers output = ∅node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputsterminal:terminal✝hEdges:right.edgeConsumers output = ∅hTerminals:right.terminalDischarges output = {terminal}⊢ (left.overlay right).terminalDischarges output = {terminal} node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputsterminal:terminal✝hEdges:right.edgeConsumers output = ∅hTerminals:right.terminalDischarges output = {terminal}⊢ (left.overlay right).edgeConsumers output = ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightoutput:ActualizedPortInstance node outputPorthOutput:output ∈ (left.overlay right).outputshOutputDisjoint:left.OutputDisjoint righthUnion:output ∈ left.outputs ∪ right.outputshRightOutput:output ∈ right.outputshNotLeft:output ∉ left.outputsterminal:terminal✝hEdges:right.edgeConsumers output = ∅hTerminals:right.terminalDischarges output = {terminal}⊢ (left.overlay right).terminalDischarges output = {terminal} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint right⊢ (left.overlay right).ClosedInputLinear intro input node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputs⊢ (left.overlay right).InputProducedExactlyOnce input node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint right⊢ (left.overlay right).InputProducedExactlyOnce input node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint right⊢ (left.overlay right).InputProducedExactlyOnce input have hUnion : input ∈ left.inputs ∪ right.inputs := node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint right⊢ (left.overlay right).ClosedPortLinear All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshEither:input ∈ left.inputs ∨ input ∈ right.inputs⊢ (left.overlay right).InputProducedExactlyOnce input cases hEither with node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshLeftInput:input ∈ left.inputs⊢ (left.overlay right).InputProducedExactlyOnce input node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshLeftInput:input ∈ left.inputsoutput:ActualizedPortInstance node outputPorthLeftOutput:output ∈ left.outputshProducer:left.inputProducers input = {output}hEdges:left.edgeConsumers output = {input}⊢ (left.overlay right).InputProducedExactlyOnce input node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshLeftInput:input ∈ left.inputsoutput:ActualizedPortInstance node outputPorthLeftOutput:output ∈ left.outputshProducer:left.inputProducers input = {output}hEdges:left.edgeConsumers output = {input}⊢ output ∈ (left.overlay right).outputsnode:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshLeftInput:input ∈ left.inputsoutput:ActualizedPortInstance node outputPorthLeftOutput:output ∈ left.outputshProducer:left.inputProducers input = {output}hEdges:left.edgeConsumers output = {input}⊢ (left.overlay right).inputProducers input = {output}node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshLeftInput:input ∈ left.inputsoutput:ActualizedPortInstance node outputPorthLeftOutput:output ∈ left.outputshProducer:left.inputProducers input = {output}hEdges:left.edgeConsumers output = {input}⊢ (left.overlay right).edgeConsumers output = {input} node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshLeftInput:input ∈ left.inputsoutput:ActualizedPortInstance node outputPorthLeftOutput:output ∈ left.outputshProducer:left.inputProducers input = {output}hEdges:left.edgeConsumers output = {input}⊢ output ∈ (left.overlay right).outputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshLeftInput:input ∈ left.inputsoutput:ActualizedPortInstance node outputPorthLeftOutput:output ∈ left.outputshProducer:left.inputProducers input = {output}hEdges:left.edgeConsumers output = {input}⊢ (left.overlay right).inputProducers input = {output} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshLeftInput:input ∈ left.inputsoutput:ActualizedPortInstance node outputPorthLeftOutput:output ∈ left.outputshProducer:left.inputProducers input = {output}hEdges:left.edgeConsumers output = {input}⊢ (left.overlay right).edgeConsumers output = {input} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshRightInput:input ∈ right.inputs⊢ (left.overlay right).InputProducedExactlyOnce input have hNotLeftInput : input ∉ left.inputs := node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint right⊢ (left.overlay right).ClosedPortLinear node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshRightInput:input ∈ right.inputshLeftInput:input ∈ left.inputs⊢ False All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshRightInput:input ∈ right.inputshNotLeftInput:input ∉ left.inputsoutput:ActualizedPortInstance node outputPorthRightOutput:output ∈ right.outputshProducer:right.inputProducers input = {output}hEdges:right.edgeConsumers output = {input}⊢ (left.overlay right).InputProducedExactlyOnce input have hNotLeftOutput : output ∉ left.outputs := node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint right⊢ (left.overlay right).ClosedPortLinear node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshRightInput:input ∈ right.inputshNotLeftInput:input ∉ left.inputsoutput:ActualizedPortInstance node outputPorthRightOutput:output ∈ right.outputshProducer:right.inputProducers input = {output}hEdges:right.edgeConsumers output = {input}hLeftOutput:output ∈ left.outputs⊢ False All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshRightInput:input ∈ right.inputshNotLeftInput:input ∉ left.inputsoutput:ActualizedPortInstance node outputPorthRightOutput:output ∈ right.outputshProducer:right.inputProducers input = {output}hEdges:right.edgeConsumers output = {input}hNotLeftOutput:output ∉ left.outputs⊢ output ∈ (left.overlay right).outputsnode:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshRightInput:input ∈ right.inputshNotLeftInput:input ∉ left.inputsoutput:ActualizedPortInstance node outputPorthRightOutput:output ∈ right.outputshProducer:right.inputProducers input = {output}hEdges:right.edgeConsumers output = {input}hNotLeftOutput:output ∉ left.outputs⊢ (left.overlay right).inputProducers input = {output}node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshRightInput:input ∈ right.inputshNotLeftInput:input ∉ left.inputsoutput:ActualizedPortInstance node outputPorthRightOutput:output ∈ right.outputshProducer:right.inputProducers input = {output}hEdges:right.edgeConsumers output = {input}hNotLeftOutput:output ∉ left.outputs⊢ (left.overlay right).edgeConsumers output = {input} node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshRightInput:input ∈ right.inputshNotLeftInput:input ∉ left.inputsoutput:ActualizedPortInstance node outputPorthRightOutput:output ∈ right.outputshProducer:right.inputProducers input = {output}hEdges:right.edgeConsumers output = {input}hNotLeftOutput:output ∉ left.outputs⊢ output ∈ (left.overlay right).outputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshRightInput:input ∈ right.inputshNotLeftInput:input ∉ left.inputsoutput:ActualizedPortInstance node outputPorthRightOutput:output ∈ right.outputshProducer:right.inputProducers input = {output}hEdges:right.edgeConsumers output = {input}hNotLeftOutput:output ∉ left.outputs⊢ (left.overlay right).inputProducers input = {output} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalleft:ActualizedPortGraph node outputPort inputPort terminalright:ActualizedPortGraph node outputPort inputPort terminalhLeft:left.ClosedPortLinearhRight:right.ClosedPortLinearhDisjoint:left.DomainDisjoint rightinput:ActualizedPortInstance node inputPorthInput:input ∈ (left.overlay right).inputshInputDisjoint:left.InputDisjoint righthOutputDisjoint:left.OutputDisjoint righthUnion:input ∈ left.inputs ∪ right.inputshRightInput:input ∈ right.inputshNotLeftInput:input ∉ left.inputsoutput:ActualizedPortInstance node outputPorthRightOutput:output ∈ right.outputshProducer:right.inputProducers input = {output}hEdges:right.edgeConsumers output = {input}hNotLeftOutput:output ∉ left.outputs⊢ (left.overlay right).edgeConsumers output = {input} All goals completed! 🐙end ActualizedPortGraph

Compiler Port-Use Witnesses

PortUseWitness is the proof-side witness produced by compiler or admission.

The finite outputs and inputs domains are intentionally explicit and caller-supplied. The open Haskell correspondence obligation is to prove that these domains are exactly the compiled graph's actualized port instances and that the executable admission path rejects source graphs that cannot construct such a witness. Without that exactness correspondence, this is only a witness checker for the domain it is given.

structure PortUseWitness (node outputPort inputPort terminal : Type) [DecidableEq node] [DecidableEq outputPort] [DecidableEq inputPort] [DecidableEq terminal] where

Actualized output port instances known to the closed graph.

outputs : Finset (ActualizedPortInstance node outputPort)

Actualized input port instances known to the closed graph.

inputs : Finset (ActualizedPortInstance node inputPort)

Exactly one use chosen for each output port instance.

outputUse : ActualizedPortInstance node outputPort → OutputPortUse (ActualizedPortInstance node inputPort) terminal

Exactly one producer chosen for each input port instance.

inputProducer : ActualizedPortInstance node inputPort → ActualizedPortInstance node outputPort

Input producers are actualized output port instances.

inputProducer_mem : ∀ input, input ∈ inputs → inputProducer input ∈ outputs

The declared input producer has an edge use to that input.

inputProducer_edge : ∀ input, input ∈ inputs → outputUse (inputProducer input) = OutputPortUse.edge input

Every edge consumer is an actualized input port instance.

edgeInput_mem : ∀ output, output ∈ outputs → ∀ input, outputUse output = OutputPortUse.edge input → input ∈ inputs

Every edge consumer points back to the output that produced it.

edgeInput_producer_eq : ∀ output, output ∈ outputs → ∀ input, outputUse output = OutputPortUse.edge input → inputProducer input = outputnamespace PortUseWitnessvariable {node outputPort inputPort terminal : Type}variable [DecidableEq node]variable [DecidableEq outputPort]variable [DecidableEq inputPort]variable [DecidableEq terminal]

Convert a compiler port-use witness into the relation-shaped graph model.

def toGraph (witness : PortUseWitness node outputPort inputPort terminal) : ActualizedPortGraph node outputPort inputPort terminal where outputs := witness.outputs inputs := witness.inputs edgeConsumers := fun output => if _hOutput : output ∈ witness.outputs then match witness.outputUse output with | OutputPortUse.edge input => {input} | OutputPortUse.terminalDischarge _terminal => ∅ else ∅ terminalDischarges := fun output => if _hOutput : output ∈ witness.outputs then match witness.outputUse output with | OutputPortUse.edge _input => ∅ | OutputPortUse.terminalDischarge terminal => {terminal} else ∅ inputProducers := fun input => if _hInput : input ∈ witness.inputs then {witness.inputProducer input} else ∅end PortUseWitnesssectionvariable {node outputPort inputPort terminal : Type} [DecidableEq node] [DecidableEq outputPort] [DecidableEq inputPort] [DecidableEq terminal]

A witnessed output is consumed by exactly one edge or terminal discharge.

theorem actualizedOutputPort_consumed_exactly_once (witness : PortUseWitness node outputPort inputPort terminal) {output : ActualizedPortInstance node outputPort} (hOutput : output ∈ witness.outputs) : witness.toGraph.OutputConsumedExactlyOnce output := node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminaloutput:ActualizedPortInstance node outputPorthOutput:output ∈ witness.outputs⊢ witness.toGraph.OutputConsumedExactlyOnce output cases hUse : witness.outputUse output with node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminaloutput:ActualizedPortInstance node outputPorthOutput:output ∈ witness.outputsinput:ActualizedPortInstance node inputPorthUse:witness.outputUse output = OutputPortUse.edge input⊢ witness.toGraph.OutputConsumedExactlyOnce output node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminaloutput:ActualizedPortInstance node outputPorthOutput:output ∈ witness.outputsinput:ActualizedPortInstance node inputPorthUse:witness.outputUse output = OutputPortUse.edge input⊢ ∃ input ∈ witness.toGraph.inputs, witness.toGraph.edgeConsumers output = {input} ∧ witness.toGraph.terminalDischarges output = ∅ node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminaloutput:ActualizedPortInstance node outputPorthOutput:output ∈ witness.outputsinput:ActualizedPortInstance node inputPorthUse:witness.outputUse output = OutputPortUse.edge input⊢ input ∈ witness.toGraph.inputsnode:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminaloutput:ActualizedPortInstance node outputPorthOutput:output ∈ witness.outputsinput:ActualizedPortInstance node inputPorthUse:witness.outputUse output = OutputPortUse.edge input⊢ witness.toGraph.edgeConsumers output = {input}node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminaloutput:ActualizedPortInstance node outputPorthOutput:output ∈ witness.outputsinput:ActualizedPortInstance node inputPorthUse:witness.outputUse output = OutputPortUse.edge input⊢ witness.toGraph.terminalDischarges output = ∅ node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminaloutput:ActualizedPortInstance node outputPorthOutput:output ∈ witness.outputsinput:ActualizedPortInstance node inputPorthUse:witness.outputUse output = OutputPortUse.edge input⊢ input ∈ witness.toGraph.inputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminaloutput:ActualizedPortInstance node outputPorthOutput:output ∈ witness.outputsinput:ActualizedPortInstance node inputPorthUse:witness.outputUse output = OutputPortUse.edge input⊢ witness.toGraph.edgeConsumers output = {input} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminaloutput:ActualizedPortInstance node outputPorthOutput:output ∈ witness.outputsinput:ActualizedPortInstance node inputPorthUse:witness.outputUse output = OutputPortUse.edge input⊢ witness.toGraph.terminalDischarges output = ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminaloutput:ActualizedPortInstance node outputPorthOutput:output ∈ witness.outputsterminal:terminal✝hUse:witness.outputUse output = OutputPortUse.terminalDischarge terminal⊢ witness.toGraph.OutputConsumedExactlyOnce output node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminaloutput:ActualizedPortInstance node outputPorthOutput:output ∈ witness.outputsterminal:terminal✝hUse:witness.outputUse output = OutputPortUse.terminalDischarge terminal⊢ ∃ terminal, witness.toGraph.edgeConsumers output = ∅ ∧ witness.toGraph.terminalDischarges output = {terminal} node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminaloutput:ActualizedPortInstance node outputPorthOutput:output ∈ witness.outputsterminal:terminal✝hUse:witness.outputUse output = OutputPortUse.terminalDischarge terminal⊢ witness.toGraph.edgeConsumers output = ∅node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminaloutput:ActualizedPortInstance node outputPorthOutput:output ∈ witness.outputsterminal:terminal✝hUse:witness.outputUse output = OutputPortUse.terminalDischarge terminal⊢ witness.toGraph.terminalDischarges output = {terminal} node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminaloutput:ActualizedPortInstance node outputPorthOutput:output ∈ witness.outputsterminal:terminal✝hUse:witness.outputUse output = OutputPortUse.terminalDischarge terminal⊢ witness.toGraph.edgeConsumers output = ∅ All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal✝:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminaloutput:ActualizedPortInstance node outputPorthOutput:output ∈ witness.outputsterminal:terminal✝hUse:witness.outputUse output = OutputPortUse.terminalDischarge terminal⊢ witness.toGraph.terminalDischarges output = {terminal} All goals completed! 🐙

A witnessed input is produced by exactly one edge.

theorem actualizedInputPort_produced_exactly_once (witness : PortUseWitness node outputPort inputPort terminal) {input : ActualizedPortInstance node inputPort} (hInput : input ∈ witness.inputs) : witness.toGraph.InputProducedExactlyOnce input := node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminalinput:ActualizedPortInstance node inputPorthInput:input ∈ witness.inputs⊢ witness.toGraph.InputProducedExactlyOnce input node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminalinput:ActualizedPortInstance node inputPorthInput:input ∈ witness.inputs⊢ witness.inputProducer input ∈ witness.toGraph.outputsnode:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminalinput:ActualizedPortInstance node inputPorthInput:input ∈ witness.inputs⊢ witness.toGraph.inputProducers input = {witness.inputProducer input}node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminalinput:ActualizedPortInstance node inputPorthInput:input ∈ witness.inputs⊢ witness.toGraph.edgeConsumers (witness.inputProducer input) = {input} node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminalinput:ActualizedPortInstance node inputPorthInput:input ∈ witness.inputs⊢ witness.inputProducer input ∈ witness.toGraph.outputs All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminalinput:ActualizedPortInstance node inputPorthInput:input ∈ witness.inputs⊢ witness.toGraph.inputProducers input = {witness.inputProducer input} All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminalinput:ActualizedPortInstance node inputPorthInput:input ∈ witness.inputs⊢ witness.toGraph.edgeConsumers (witness.inputProducer input) = {input} node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminalinput:ActualizedPortInstance node inputPorthInput:input ∈ witness.inputshProducerMem:witness.inputProducer input ∈ witness.outputs⊢ witness.toGraph.edgeConsumers (witness.inputProducer input) = {input} node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminalinput:ActualizedPortInstance node inputPorthInput:input ∈ witness.inputshProducerMem:witness.inputProducer input ∈ witness.outputshProducerEdge:witness.outputUse (witness.inputProducer input) = OutputPortUse.edge input⊢ witness.toGraph.edgeConsumers (witness.inputProducer input) = {input} All goals completed! 🐙

Two edge outputs cannot produce the same input unless they are the same output.

theorem compiledPortUseWitness_edge_input_uniqueProducer (witness : PortUseWitness node outputPort inputPort terminal) {left right : ActualizedPortInstance node outputPort} {input : ActualizedPortInstance node inputPort} (hLeftOutput : left ∈ witness.outputs) (hRightOutput : right ∈ witness.outputs) (hLeftEdge : witness.outputUse left = OutputPortUse.edge input) (hRightEdge : witness.outputUse right = OutputPortUse.edge input) : left = right := node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminalleft:ActualizedPortInstance node outputPortright:ActualizedPortInstance node outputPortinput:ActualizedPortInstance node inputPorthLeftOutput:left ∈ witness.outputshRightOutput:right ∈ witness.outputshLeftEdge:witness.outputUse left = OutputPortUse.edge inputhRightEdge:witness.outputUse right = OutputPortUse.edge input⊢ left = right node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminalleft:ActualizedPortInstance node outputPortright:ActualizedPortInstance node outputPortinput:ActualizedPortInstance node inputPorthLeftOutput:left ∈ witness.outputshRightOutput:right ∈ witness.outputshLeftEdge:witness.outputUse left = OutputPortUse.edge inputhRightEdge:witness.outputUse right = OutputPortUse.edge inputhLeftProducer:witness.inputProducer input = left⊢ left = right node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminalleft:ActualizedPortInstance node outputPortright:ActualizedPortInstance node outputPortinput:ActualizedPortInstance node inputPorthLeftOutput:left ∈ witness.outputshRightOutput:right ∈ witness.outputshLeftEdge:witness.outputUse left = OutputPortUse.edge inputhRightEdge:witness.outputUse right = OutputPortUse.edge inputhLeftProducer:witness.inputProducer input = lefthRightProducer:witness.inputProducer input = right⊢ left = right calc left = witness.inputProducer input := node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminalleft:ActualizedPortInstance node outputPortright:ActualizedPortInstance node outputPortinput:ActualizedPortInstance node inputPorthLeftOutput:left ∈ witness.outputshRightOutput:right ∈ witness.outputshLeftEdge:witness.outputUse left = OutputPortUse.edge inputhRightEdge:witness.outputUse right = OutputPortUse.edge inputhLeftProducer:witness.inputProducer input = lefthRightProducer:witness.inputProducer input = right⊢ left = witness.inputProducer input All goals completed! 🐙 _ = right := hRightProducer

A supplied port-use witness establishes closed linearity for its own graph domain.

theorem portUseWitness_toGraph_closedPortLinear (witness : PortUseWitness node outputPort inputPort terminal) : witness.toGraph.ClosedPortLinear := node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminal⊢ witness.toGraph.ClosedPortLinear node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminal⊢ witness.toGraph.ClosedOutputLinearnode:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminal⊢ witness.toGraph.ClosedInputLinear node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminal⊢ witness.toGraph.ClosedOutputLinear intro output node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminaloutput:ActualizedPortInstance node outputPorthOutput:output ∈ witness.toGraph.outputs⊢ witness.toGraph.OutputConsumedExactlyOnce output have hWitnessOutput : output ∈ witness.outputs := node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminal⊢ witness.toGraph.ClosedPortLinear All goals completed! 🐙 All goals completed! 🐙 node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminal⊢ witness.toGraph.ClosedInputLinear intro input node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminalinput:ActualizedPortInstance node inputPorthInput:input ∈ witness.toGraph.inputs⊢ witness.toGraph.InputProducedExactlyOnce input have hWitnessInput : input ∈ witness.inputs := node:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalwitness:PortUseWitness node outputPort inputPort terminal⊢ witness.toGraph.ClosedPortLinear All goals completed! 🐙 All goals completed! 🐙end

Selected-Branch Preservation

Port-use graph for the selected arm of a select(...) actualization.

The domain-exact projection from a runtime selected fragment into this graph is a separate correspondence obligation; this structure records the local witness once supplied.

structure SelectedActualizedPortGraph (node arm outputPort inputPort terminal : Type) [DecidableEq node] [DecidableEq outputPort] [DecidableEq inputPort] [DecidableEq terminal] {family : LatentBranchFamily node arm} (actualize : SelectActualize family) where

Port consumer and producer graph contributed by the selected branch.

graph : ActualizedPortGraph node outputPort inputPort terminal

Every selected output belongs to the selected latent fragment's node set.

outputsWithinSelectedFragment : ∀ output, output ∈ graph.outputs → output.node ∈ actualize.selectedFragmentNodes

Every selected input belongs to the selected latent fragment's node set.

inputsWithinSelectedFragment : ∀ input, input ∈ graph.inputs → input.node ∈ actualize.selectedFragmentNodessectionvariable {node arm outputPort inputPort terminal : Type} [DecidableEq node] [DecidableEq outputPort] [DecidableEq inputPort] [DecidableEq terminal] {family : LatentBranchFamily node arm} {actualize : SelectActualize family}

Selected output witnesses are tied to the chosen latent branch fragment.

theorem selectActualize_selectedOutputs_within_selectedFragment (selected : SelectedActualizedPortGraph node arm outputPort inputPort terminal actualize) {output : ActualizedPortInstance node outputPort} (hOutput : output ∈ selected.graph.outputs) : output.node ∈ actualize.selectedFragmentNodes := selected.outputsWithinSelectedFragment output hOutput

Selected input witnesses are tied to the chosen latent branch fragment.

theorem selectActualize_selectedInputs_within_selectedFragment (selected : SelectedActualizedPortGraph node arm outputPort inputPort terminal actualize) {input : ActualizedPortInstance node inputPort} (hInput : input ∈ selected.graph.inputs) : input.node ∈ actualize.selectedFragmentNodes := selected.inputsWithinSelectedFragment input hInput

Current outputs outside the selected fragment are disjoint from selected outputs.

theorem selectActualize_currentOutputs_disjoint_selectedOutputs (current : ActualizedPortGraph node outputPort inputPort terminal) (selected : SelectedActualizedPortGraph node arm outputPort inputPort terminal actualize) (hCurrentOutsideSelected : ∀ output, output ∈ current.outputs → output.node ∉ actualize.selectedFragmentNodes) : ActualizedPortGraph.OutputDisjoint current selected.graph := node:Typearm:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalfamily:LatentBranchFamily node armactualize:SelectActualize familycurrent:ActualizedPortGraph node outputPort inputPort terminalselected:SelectedActualizedPortGraph node arm outputPort inputPort terminal actualizehCurrentOutsideSelected:∀ output ∈ current.outputs, output.node ∉ actualize.selectedFragmentNodes⊢ current.OutputDisjoint selected.graph intro output node:Typearm:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalfamily:LatentBranchFamily node armactualize:SelectActualize familycurrent:ActualizedPortGraph node outputPort inputPort terminalselected:SelectedActualizedPortGraph node arm outputPort inputPort terminal actualizehCurrentOutsideSelected:∀ output ∈ current.outputs, output.node ∉ actualize.selectedFragmentNodesoutput:ActualizedPortInstance node outputPorthCurrentOutput:output ∈ current.outputs⊢ output ∈ selected.graph.outputs → False node:Typearm:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalfamily:LatentBranchFamily node armactualize:SelectActualize familycurrent:ActualizedPortGraph node outputPort inputPort terminalselected:SelectedActualizedPortGraph node arm outputPort inputPort terminal actualizehCurrentOutsideSelected:∀ output ∈ current.outputs, output.node ∉ actualize.selectedFragmentNodesoutput:ActualizedPortInstance node outputPorthCurrentOutput:output ∈ current.outputshSelectedOutput:output ∈ selected.graph.outputs⊢ False node:Typearm:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalfamily:LatentBranchFamily node armactualize:SelectActualize familycurrent:ActualizedPortGraph node outputPort inputPort terminalselected:SelectedActualizedPortGraph node arm outputPort inputPort terminal actualizehCurrentOutsideSelected:∀ output ∈ current.outputs, output.node ∉ actualize.selectedFragmentNodesoutput:ActualizedPortInstance node outputPorthCurrentOutput:output ∈ current.outputshSelectedOutput:output ∈ selected.graph.outputshSelectedNode:output.node ∈ actualize.selectedFragmentNodes⊢ False All goals completed! 🐙

Current inputs outside the selected fragment are disjoint from selected inputs.

theorem selectActualize_currentInputs_disjoint_selectedInputs (current : ActualizedPortGraph node outputPort inputPort terminal) (selected : SelectedActualizedPortGraph node arm outputPort inputPort terminal actualize) (hCurrentOutsideSelected : ∀ input, input ∈ current.inputs → input.node ∉ actualize.selectedFragmentNodes) : ActualizedPortGraph.InputDisjoint current selected.graph := node:Typearm:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalfamily:LatentBranchFamily node armactualize:SelectActualize familycurrent:ActualizedPortGraph node outputPort inputPort terminalselected:SelectedActualizedPortGraph node arm outputPort inputPort terminal actualizehCurrentOutsideSelected:∀ input ∈ current.inputs, input.node ∉ actualize.selectedFragmentNodes⊢ current.InputDisjoint selected.graph intro input node:Typearm:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalfamily:LatentBranchFamily node armactualize:SelectActualize familycurrent:ActualizedPortGraph node outputPort inputPort terminalselected:SelectedActualizedPortGraph node arm outputPort inputPort terminal actualizehCurrentOutsideSelected:∀ input ∈ current.inputs, input.node ∉ actualize.selectedFragmentNodesinput:ActualizedPortInstance node inputPorthCurrentInput:input ∈ current.inputs⊢ input ∈ selected.graph.inputs → False node:Typearm:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalfamily:LatentBranchFamily node armactualize:SelectActualize familycurrent:ActualizedPortGraph node outputPort inputPort terminalselected:SelectedActualizedPortGraph node arm outputPort inputPort terminal actualizehCurrentOutsideSelected:∀ input ∈ current.inputs, input.node ∉ actualize.selectedFragmentNodesinput:ActualizedPortInstance node inputPorthCurrentInput:input ∈ current.inputshSelectedInput:input ∈ selected.graph.inputs⊢ False node:Typearm:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalfamily:LatentBranchFamily node armactualize:SelectActualize familycurrent:ActualizedPortGraph node outputPort inputPort terminalselected:SelectedActualizedPortGraph node arm outputPort inputPort terminal actualizehCurrentOutsideSelected:∀ input ∈ current.inputs, input.node ∉ actualize.selectedFragmentNodesinput:ActualizedPortInstance node inputPorthCurrentInput:input ∈ current.inputshSelectedInput:input ∈ selected.graph.inputshSelectedNode:input.node ∈ actualize.selectedFragmentNodes⊢ False All goals completed! 🐙

Selected-arm actualization preserves closed port linearity under namespace freshness.

theorem selectActualize_preserves_closedPortLinearity (current : ActualizedPortGraph node outputPort inputPort terminal) (selected : SelectedActualizedPortGraph node arm outputPort inputPort terminal actualize) (hCurrent : current.ClosedPortLinear) (hSelected : selected.graph.ClosedPortLinear) (hCurrentOutputsOutsideSelected : ∀ output, output ∈ current.outputs → output.node ∉ actualize.selectedFragmentNodes) (hCurrentInputsOutsideSelected : ∀ input, input ∈ current.inputs → input.node ∉ actualize.selectedFragmentNodes) : (current.overlay selected.graph).ClosedPortLinear := node:Typearm:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalfamily:LatentBranchFamily node armactualize:SelectActualize familycurrent:ActualizedPortGraph node outputPort inputPort terminalselected:SelectedActualizedPortGraph node arm outputPort inputPort terminal actualizehCurrent:current.ClosedPortLinearhSelected:selected.graph.ClosedPortLinearhCurrentOutputsOutsideSelected:∀ output ∈ current.outputs, output.node ∉ actualize.selectedFragmentNodeshCurrentInputsOutsideSelected:∀ input ∈ current.inputs, input.node ∉ actualize.selectedFragmentNodes⊢ (current.overlay selected.graph).ClosedPortLinear node:Typearm:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalfamily:LatentBranchFamily node armactualize:SelectActualize familycurrent:ActualizedPortGraph node outputPort inputPort terminalselected:SelectedActualizedPortGraph node arm outputPort inputPort terminal actualizehCurrent:current.ClosedPortLinearhSelected:selected.graph.ClosedPortLinearhCurrentOutputsOutsideSelected:∀ output ∈ current.outputs, output.node ∉ actualize.selectedFragmentNodeshCurrentInputsOutsideSelected:∀ input ∈ current.inputs, input.node ∉ actualize.selectedFragmentNodeshOutputDisjoint:current.OutputDisjoint selected.graph⊢ (current.overlay selected.graph).ClosedPortLinear node:Typearm:TypeoutputPort:TypeinputPort:Typeterminal:Typeinst✝³:DecidableEq nodeinst✝²:DecidableEq outputPortinst✝¹:DecidableEq inputPortinst✝:DecidableEq terminalfamily:LatentBranchFamily node armactualize:SelectActualize familycurrent:ActualizedPortGraph node outputPort inputPort terminalselected:SelectedActualizedPortGraph node arm outputPort inputPort terminal actualizehCurrent:current.ClosedPortLinearhSelected:selected.graph.ClosedPortLinearhCurrentOutputsOutsideSelected:∀ output ∈ current.outputs, output.node ∉ actualize.selectedFragmentNodeshCurrentInputsOutsideSelected:∀ input ∈ current.inputs, input.node ∉ actualize.selectedFragmentNodeshOutputDisjoint:current.OutputDisjoint selected.graphhInputDisjoint:current.InputDisjoint selected.graph⊢ (current.overlay selected.graph).ClosedPortLinear All goals completed! 🐙endend Cortex.Wire